; []===========================================================[] ; ; NOTICE: THIS PROGRAM BELONGS TO AWARD SOFTWARE INTERNATIONAL(R) ; INC. IT IS CONSIDERED A TRADE SECRET AND IS NOT TO BE ; DIVULGED OR USED BY PARTIES WHO HAVE NOT RECEIVED ; WRITTEN AUTHORIZATION FROM THE OWNER. ; ; []===========================================================[] ; ;============================================================================= ; FILE: DMI_CT.INC ; ; DESC: Chipset Specific BIOS Support ; CHIPSET: VIA VT82C597 ; ; BY: Tim Markey, Award Software Intl., Inc. ; DATE: 06/06/96 ;============================================================================= ;---------------------------------------------------------------------------- ;Rev Date Name Description ;---------------------------------------------------------------------------- ;R01 11/11/98 STV Def Memory Module Info (Type 06) show Bank for RAS# 0&1 ;R00 08/15/98 RIC Initialization. ;---------------------------------------------------------------------------- ;============================================================================= ; FUNC: CT_GET_DMI_MEMORY_TYPE ; ; DESC: Get the memory type for this chipset ; ; IN: CL - Bank ; OUT: AX - Memory type define as: ; MEM_TYPES_OTHER ; MEM_TYPES_UNKNOWN ; MEM_TYPES_STANDARD ; MEM_TYPES_FAST_PAGE ; MEM_TYPES_EDO ; MEM_TYPES_PARITY ; MEM_TYPES_ECC ; MEM_TYPES_SIMM ; MEM_TYPES_DIMM ; ;============================================================================= ct_get_dmi_memory_type proc uses bx dx push cx call ct_get_dmi_mem_size cmp ax, MEM_MAX_MODULE_000MB jz short No_DRAM_Plug push cx mov cx, VT692+60h F000_call Get_Ct ; get DRAM type from RX60 pop cx ifdef Show_DMI_Mem_Row ;R01 and cl,0FEh ; Mask bit0 else shl cx,1 ;R01 endif ;Show_DMI_Mem_Row ;R01 ; CL = 0 : Bank 0/1 ; CL = 2 : Bank 2/3 ; CL = 4 : Bank 4/5 ; CL = 6 : Bank 6/7 shr al, cl and al, 00000011b ; Select test bit mov cl, al mov ax,MEM_TYPES_FAST_PAGE ; 00 = Fast page mode DRAM cmp cl, 00000000b je short @F mov ax,MEM_TYPES_EDO ; 01 = EDO DRAM cmp cl, 00000001b je short @F mov ax,MEM_TYPES_SDRAM + MEM_TYPES_DIMM ; 11 = SDRAM cmp cl, 00000011b je short @F No_DRAM_Plug: mov ax,MEM_TYPES_UNKNOWN @@: pop cx ret ct_get_dmi_memory_type endp ;R01 start ifndef Show_DMI_Mem_Row Ct_Get_Mem_RAS_Value proc push cx ;Save CL point to This Bank xor ax,ax mov si,cx mov al,cs:Mem_Bank_Connection_Table[si] pop cx ret Ct_Get_Mem_RAS_Value Endp get_base_row proc push bx mov cx, VT692+5Ah ; AX = base DRAM Row 0 Boundary register cmp bx,6 jb short Not_Row_6_7 mov cx,VT692+50h Not_Row_6_7: add cx,bx ; CX = DRAM Row F000_call Get_Ct ; get byte from PCI space into AL (DX modified) pop bx ret get_base_row endp ;---------------------------------------------------------- ;Func : Ct_Get_Mem_Size_Each_Row ;IN : BX -- Which Row ;OUT : CX -- Each Row MEM Size ; (EX: Row3 MEM Size = DRB3-DRB2 ; DRB= DRAM Row Boundary) ;---------------------------------------------------------- Ct_Get_Mem_Size_Each_Row proc call get_base_row .if bx == 00h mov cx,ax ret .else push ax call get_base_row dec cx F000_Call Get_Ct mov cx,ax pop ax .if cx > ax sub cx,ax .else sub ax,cx mov cx,ax .endif .endif ret Ct_Get_Mem_Size_Each_Row endp ;---------------------------------------------------------- ;Func : Ct_Get_Mem_Size_Each_Slot ;IN : CL - Bank ;OUT : AX - Size (8M Unit) ;---------------------------------------------------------- Ct_Get_Mem_Size_Each_Slot proc push cx call Ct_Get_Mem_RAS_Value ; Get MEM_Bank_Connetcxx Value to AX mov bx,ax ; Get DRB value of one RAS push bx and bl,00001111b call Ct_Get_Mem_Size_Each_Row ;Get CX pop bx push cx and bl,11110000b ;Mask shr bl,4 call Ct_Get_Mem_Size_Each_Row mov ax,cx pop cx add ax,cx ; Two Rows total amount pop cx ret Ct_Get_Mem_Size_Each_Slot endp endif ;Show_DMI_Mem_Row ;R01 end ;============================================================================= ; FUNC: CT_GET_DMI_MEM_SIZE ; ; DESC: Return Memory Size for Bank ; ; IN: CL - Bank ; OUT: AL - Size (Memory size = 2 ^ AL MB) ;============================================================================= ct_get_dmi_mem_size proc uses bx cx dx ;R01 start ifndef Show_DMI_Mem_Row push cx call Ct_Get_Mem_Size_Each_Slot Get_DRAM_Size: cmp al,0 je short No_DRAM xor cx,cx cmp al,1 je short @F .repeat shr al,1 inc cx .until al & 1 @@: add cx,3 ; DRB 8M Unit mov ax,cx pop cx ret No_DRAM: mov ax,MEM_MAX_MODULE_000MB pop cx ret else ;R01 end xor ch,ch ; clear CH push cx ; save bank number mov ax, VT692+5Ah ; AX = base DRAM Row 0 Boundary register cmp cl,6 jb short Not_Row_6_7_ mov ax,VT692+50h Not_Row_6_7_: add ax,cx ; AX = DRAM Row CL mov cx,ax ; CX = DRAM Row F000_call Get_Ct ; get byte from PCI space into AL (DX modified) pop cx ; restore bank number cmp cl, 00h ; if not first bank je short @F mov bx,ax ; save bank sum total mov ax, VT692+5Ah ; AX = base DRAM Row 0 Boundary register sub cl,1 ; get previous bank sum cmp cl,6 jb short Not_Row_6_7 mov ax,VT692+50h Not_Row_6_7: add ax,cx ; AX = DRAM Row (Bank-1) mov cx,ax ; CX = DRAM Row (Bank-1) F000_call Get_Ct ; get byte from PCI space into AL (DX modified) sub bx,ax ; BX = Memory Size for Bank mov ax,bx ; return AX = Bank Size @@: ; now convert to DMI memory module size format (2**X) cmp ax, 00h jne short @F mov ax,MEM_MAX_MODULE_000MB ret @@: mov cx, 03h @@: ; repeart test ax until to 1 then exit cmp ax, 01h ; test for bit zero set jle short @F shr ax,1 ; Shift AX by 1 inc cx ; increment count in CX jmp short @B @@: mov ax,cx ; AX contains memory module size ret endif ;Show_DMI_Mem_Row ;R01 ct_get_dmi_mem_size endp ;============================================================================= ; FUNC: CT_GET_DMI_MEM_SPEED ; ; DESC: Return Memory Speed for Bank ; ; IN: CL - Bank ; OUT: AL - Speed (unit is "ns") ;============================================================================= ct_get_dmi_mem_speed proc uses dx ifdef DMI_SPEED_UNDETERMINEABLE push si call ct_get_dmi_memory_type cmp ax,MEM_TYPES_SDRAM mov al,10 je short SDRAM_ cmp cl,1 ja short Not_Bank01 mov si,offset Bank_01_DRAM_Timing_Item jmp short Get_DRAM_Timing_Item Not_Bank01: cmp cl,3 ja short Not_Bank23 mov si,offset Bank_23_DRAM_Timing_Item jmp short Get_DRAM_Timing_Item Not_Bank23: cmp cl,5 ja short Not_Bank45 mov si,offset Bank_45_DRAM_Timing_Item jmp short Get_DRAM_Timing_Item Not_Bank45: mov si,offset Bank_67_DRAM_Timing_Item Get_DRAM_Timing_Item: F000_call GetItem_Value cmp al,01 mov al,60 jz short SDRAM_ mov al,70 SDRAM_: pop si endif; DMI_SPEED_UNDETERMINEABLE ret ct_get_dmi_mem_speed endp ;============================================================================= ; FUNC: CT_GET_DMI_MEM_INTERLEAVE ; ; DESC: Return Memory Current Interleave ; ; IN: CL - ; OUT: AL - 01h : Other ; 02h : Unknown ; 03h : One Way Interleave ; 04h : Two Way Interleave ; 05h : Four Way Interleave ; 06h : Eight Way Interleave ; 07h : Sixteen Way Interleave ;============================================================================= ct_get_dmi_mem_interleave proc uses dx ifdef Have_BankInterleave_Item push si mov si,offset SDRAM_BK_Item F000_call GetItem_Value ;al: 0=Disable,1=2Bank,2=4Bank. add al,3 pop si else; Have_BankInterleave_Item mov al,03h endif; Have_BankInterleave_Item ret ct_get_dmi_mem_interleave endp ;============================================================================= ; FUNC: CT_GET_DMI_MEM_ERROR_DETECTING ; ; DESC: Return Memory Error Detecting Method ; ; IN: CL - ; OUT: AL - 01h : Other ; 02h : Unknown ; 03h : None ; 04h : 8-bit Parity ; 05h : 32-bit ECC ; 06h : 64-bit ECC ; 07h : 128-bit ECC ; 08h : CRC ;for SMBIOS V2.1 ;============================================================================= ct_get_dmi_mem_error_detecting proc uses dx ifdef NO_PARITY_ITEM mov al,03h else; NO_PARITY_ITEM push si mov si,offset Parity_Item F000_call GetItem_Value ;al: 0=Disable,1=Enable. mov cl,al mov al,3 shl al,cl pop si endif; NO_PARITY_ITEM ret ct_get_dmi_mem_error_detecting endp ;============================================================================= ; FUNC: CT_GET_DMI_CACHE_CONFIG ; ; DESC: Get the memory type for this chipset ; ; IN: CL - Bank ; OUT: AX - Bits 15:10 Reserved, must be zero ; Bits 9:8 Operational Mode ; 00b Write Through ; 01b Write Back ; 10b Varies with Memory Address ; 11b Unknown ; Bit 7 Enable/Disable(at boot time) ; 1b Enable ; 0b Disable ; Bits 6:5 Location,relative to the CPU ; module: ; 00b Internal ; 01b External ; 10b Reserved ; 11b Unknown ; Bit 4 Reserved,must be zero ; Bit 3 Cache Socketed ; 1b Socketed ; 0b Not Socketed ; Bits 2:0 Cache Leave - 1 through 8,e.g ; an L1 cache would use value 000b and ; an L3 cache would use 010b. ;============================================================================= ct_get_dmi_cache_config proc uses bx dx ret ct_get_dmi_cache_config endp