; []===========================================================[] ; ; NOTICE: THIS PROGRAM BELONGS TO AWARD SOFTWARE INTERNATIONAL(R) ; INC. IT IS CONSIDERED A TRADE SECRET AND IS NOT TO BE ; DIVULGED OR USED BY PARTIES WHO HAVE NOT RECEIVED ; WRITTEN AUTHORIZATION FROM THE OWNER. ; ; []===========================================================[] ; ;---------------------------------------------------------------------------- ;Rev Date Name Description ;---------------------------------------------------------------------------- ;R145B 03/17/99 RCH Added more CPU models support for Rise. It include ; 052x, 059x ;R151 03/15/99 RAY Seperate this file into different include files ; according to different CPU level. ; ; There will be 4 new files: CPU3486.ASM ; CPU586.ASM ; CPU686.ASM ; CPUGX86.ASM ; ;R149 03/10/99 RCH Added a setup item for choosing CPUID instruction ; for Cyrix 6x86/MII CPU. ; 1. The system can not install Netware 5.0 if CPUID ; is enabled. ; 2. Software can not use MMX instruction if CPUID ; is disabled. ;R147A 03/10/99 RCH Added 90Mhz host clock table for K6 & M2 CPU to fix ; wrong Prating display for M2 90x3 ;R128B 03/03/99 JKY Fixed code mistake. ;R128A 03/02/99 JKY Added read L2 cache size determine Mobile pentium II ; or Celeron for CPUID=66A. ; L2 cache = 128k --- Celeron ; = 256k --- Mobile pentium II (Dixon) ;R148 02/24/99 RAY Upon Cyrix request, change the P-rating of 100*2.5 ; from P333 to P366 and from P366 to P380 for 100*3.0 ;R147 02/22/99 RCH Rewrite CPU clock detection routine for K6-2, K6-3 & ; M2 CPUs to support clock over 512Mhz ;R146 02/22/99 RCH Fixed wrong CPU clock display for AMD K6-2 500MHz CPU ; (100x5) and 457Mhz(83x5.5) ;R145A 02/22/99 RCH Display "Rise mP6(TM) II" for Rise 058x CPU. ;R145 02/10/99 RCH Support Rise mP6-2 CPU with 058x CPUID ;R102A 02/08/99 RCH Change CPU name display for AMD-K6-3 from ; "AMD-K6(tm)-3" to "AMD-K6(tm)-III". ;R141A 02/03/99 RAY Fixed compiler error if NO_PRATING_DISPLAY is defined ;R140A 02/02/99 RCH Pentium III CPU processor number selection become ; stanadard feature. BIOS will hide the CMOS setup ; if the plugged CPU is not Pentium III. ;R144 01/30/99 RCH Added AMD/K7 CPU support. ;R143 01/30/99 RCH No "MMX" display for P6 class CPUs. ;R142 01/28/99 RAY Support IDT WinChip 3. ; Also, upon their request, do not shot "-3D" any more. ;R141 01/28/99 RAY Move the codes of showing PR Ratings to XGROUP ;R140 01/28/99 RCH Support "Processor Number CPU" for Penitum III series ; CPUs. Switch "PSN_CMOS" & "PSN_CMOS_BIT" are required. ; ;R139 01/27/99 RAY Support IDT WinChip 2A which supports up to 100Mhz ; external frequency. Also display PR rating instead ; of MHz for this chip. ; ;R138 01/27/99 RCH Added CPU display for SGS-Thomson STPC platform ;R106A 01/26/99 RCH Fixed Intel 486DX2 non-SMI CPU can not be detected ; properly on 486 platform. ;R137B 01/19/99 RCH Show "Pentium III Xeon" instead of "Penitum III" for ; Slot 2 CPU. ;R137A 01/13/99 RAY Name "Pentiem III" also applies to CPU steppings ; which is greater than 067x. Thus Xeon CPU will ; also be shown as "Pentiem III" ;R137 01/12/99 RAY Show "Pentium III" instead of "Pentium II" for ; Katmai CPU (stepping 067x) ;R136 01/07/99 TNY Fix 433Mhz CPU show error(432MHz). ;R135 01/07/99 RCH Added host clock 90Mhz & 95Mhz support for Cyrix & ; Rise CPU Prating display ;R134 12/31/98 JSN Fixed post hang up at 0Ah when Cyrix MII 333GP CPU(66X4) ; plugged. ;R133 12/30/98 RIC Add the table support of AMD CPU clock over 100MHZ '. ; (105/110/115/120/124/133). ;R132 12/29/98 RCH Reserve a byte space for storing host clock frequency ; of P6 CPU. Some chipsets need this information for ; timing programming. ;R131 12/18/98 LAW added Public P6_CLKRATIO ; 12/14/98 Intel P6 CPUIDs Information Update: ; 063X - Pentium II , model 3 ; 065X - Pentium II , model 5 , Deschutes ; 066X - Celeron , Mendocino ; 067X - Katmai , Tanner ; 068X - Coppermine , Cascade ;R130 12/04/98 RIC Update and Changed Cyrix MII CPU Prating: ; PR233 to PR266 for 66x3(200MHz) ; PR350 to PR366 for 100x3(300MHz)/83x3.5(292MHz)/75x4(300MHz) ; PR233 to PR200 for 50x3.5(175MHz) ;R129 12/04/98 PAL Added host clock 117,129 & 138Mhz support ;R128 11/27/98 JKY Change CPU ID=066A display 'Mobile Pentium II' ;R127 11/25/98 MIL Added Display String "Cyrix MXi" for Cyrix MXi CPU. ;R126 11/25/98 ADS Support customer requested AMD CPU clock over 100MHZ 's ; CPU CLOCK show . ;R125 11/24/98 JDN Fix STR Fail, Add hook Ct_OPEN_SM_RAM,Ct_CLOSE_SM_RAM ;R124 11/17/98 TNY Add Rise mP6 CPU P-Rating showing. ;R105B 11/17/98 RCH More modifications for Rise mP6 CPU support for new ; revision update. This new CPU support RDTSC instruction ; Rise also request Performace Rating display instead ; of real frequency. ;R123A 11/13/98 TNY Moved from CPUPOST.ASM ;R123 11/09/98 TNY Move measure cpu speed hook for old 586 CPU to xfile.asm ; , because this area is cacheable. ;R122 11/05/98 LAW add "No_Need_VideoCache" ;R66A 10/27/98 RCH Fixed wrong decompressed data size return by changing ; decompress method from real mode to protected mode. ; It waste too much time, if the CPU micro code is not ; supported in BIOS. ;R121 10/14/98 RAY Add 95Mhz host clock table for AMD K6-2 ;R112D 10/14/98 TNY Fix AMD 5.5 ratio CPU show 363MHz (366MHz is right) ;R120 10/09/98 RCH Support both slot 1 & slot 2 micro codes in one BIOS, ; Auto-detect CPU type and load proper micro code if ; switch "SUPPORT_SLOT1_AND_SLOT2" is used. Please note ; this feature is available only for new Xeon CPU. ; the old Xeon did implment bit 52-50 in MSR BBL_CR_OVRD ; ;R112C 10/08/98 RCH Fixed wrong CPU frequency display for AMD K6-2 model ; 8 and later. ;R119 10/08/98 RAY Change some instructions from "jmp short ???" to ; "jmp ???". MASM 6.x will automatically optimize ; the length of the code thus "short" will no longer ; needed ! ; ;R118 10/08/98 RAY Support K6-2 model 8's write allocation in which ; the write allocation limit bits are different from ; model 7 & before ; ;R117 10/07/98 JDN Add code for save P6 Patch code ;R116 10/01/98 PAL Added host clock 95MHz for ICS4858 Support ;R115 09/29/98 KVN Release DMI and ESCD pool in flash ROM when not define ; "ESCD_SUPPORT" and "FLASH_SUPPORT" in BIOS.CFG ;R114 09/24/98 RCH The Intel/Pentium II CPU will destroy register EBX while ; CPUID instruction(with EAX=1) is executed that cause ; the cacheable memory size is limited to 512Mb and ; system performance drop dramatically if installed ; DRAM size bigger than 512Mb ;R112B 09/17/98 RCH Fixed compliation error for 486 platforms ;R113 09/14/98 JSN Added 83x3.5(290Mhz)/83x4.5(373Mhz) support for AMD/K6 CPU. ;R112A 09/10/98 TNY Fix coding error. ;R112 09/09/98 TNY Support bus clock ration of AMD model 8 CPU. ;R70B 09/09/98 RCH Functional change for IDT/C6 CPU write combing ;R111 09/07/98 RCH Added CPUID 068x support for future Pentium II series ;R91A 09/04/98 RIC Add "Disable_WT_ALLOC_When_Cyrix_83_x3" define. ;R110 09/04/98 RCH Support Pentium II OverDrive Processor with CPUID ; 163x. CPU name display as "Penitum II ODP-MMX" ;R109 09/03/98 TNY Add "Higher_240MHz_Tbl" for 2a59iz1c.cfg ;R108 08/26/98 PAL Added host clock 124,150 & 140Mhz support for 100Mhz ;R107A 08/18/98 RCH More fix for the 15-16MB memory hole still cacheable ; The 15-16MB memory should be programmed as UC. ;R107 08/14/98 RCH Fixed 15-16MB memory hole not working if P6 or P II ; CPU is used and L1/L2 cache is enabled ;R105A 08/12/98 RCH Don't display "MMX" for Rise/mP6 CPU ;R54A 08/06/98 MIL Added tolerance value for difference clock generator ; cause Cyrix MediaGXm CPU detect error . ;R106 08/06/98 RCH Set CPU type to Intel/P6 if the CPUID is not found ; for P6 class platform to prevent BIOS hang up in POST ; for new Intel slot1 CPU that the CPUID is not in ; the CPU table. ;R105 08/05/98 RCH Added Rise/mP6 CPU support. This CPU is almost same ; as Pentium. The difference is CPUID. So use same ; CPU CMOS value but display different CPU name. The ; current mP6 don't support Time Stamp Counter(RDTSC) ; instruction. It will be supported in next version. ;R104 07/29/98 ATY Special Show IBM of string for Costomer of request. ;R103 07/28/98 RCH Fixed system reset after shutdown from Netware SMP ; OS if the CPU ID is 0651H for MP platform, due to ; data stored in segment 4100H was destoried by P6 ; micro codes that are decompressed to 4000:0 ;R102 07/28/98 RCH Added K6 CPU display for model 059x with string ; "AMD-K6(tm)-3". This CPU support 100Mhz host clock ; and 256Kb backside L2 cache. ;R70A 07/14/98 AVN Added code for programming C6 WinChip2 "write combing". ;R101 07/14/98 RCH Change host clock value from 66Mhz to 75Mhz if the ; measured frequency is 225Mhz for Pentium platform ;R98A 07/03/98 AVN Fix R98 cause 486 BIOS compilation error ;R100 07/03/98 JSN Changed Cyrix MII CPU Prating: ; PR266 to PR233 for 60x3.5(210MHz) ;R99 07/02/98 TNY Add "P6_NO_68MHz" option. ;R98 07/02/98 AVN Added IDTC6 WinChip 2 CPU auto core-to-bus clock ratio ; by referencing register FCR4 which will reflect the ; clock ratio ;R95A 06/29/98 MIL Fixed System hang-up during WinBench 98 "CPUmark32" ; test, because we change Cyrix MediaGXm Series CPU ; detection algorithm. ;R97A 06/29/98 RCH Identify CPU Mendocino and Penitum II by CPUID with ; 066XH. ;R97 06/25/98 RCH Added Celeron 0660H CPUID with 128Kb L2 cache, due to ; L2 cache existing this CPU will show "Pentium II". ; Need more information from Intel to have correct name. ;R88B 06/18/98 RCH Display both Cyrix MII and IBM/6x86MX CPU names for ; M II CPU. ;R96 06/08/98 RCH Support L2 cache size up to 2MB for Pentium II/Pro ; CPUs. ;R95 06/01/98 MIL Change Cyrix MediaGXm Series CPU detection algorithm. ; Because the GXm CPU support "RDTSC" instruction. ;R94 05/28/98 RAY Support IDT WinChip CPU with stepping 0580h ; - show "IDT WinChip 2" or "IDT WinChip 2-3D" depends ; on whether 3D feature exist ;R93 05/28/98 JSN Add 'Disable_K6_WCDE' defination. ;R92 05/27/98 JSN Some chipset will assert KENJ during CPU single local ; memory write cycle ,so add 'Disable_K6_Write_Allocate' ; defination. ;R78A 05/26/98 RAY Show "AMD-K6(tm)-2" instead of "AMD-K6 3D" by requst ; of AMD ;R91 05/22/98 RIC Add "Disable_WT_ALLOC_When_Cyrix_PR266" define. ;R89A 05/19/98 RCH Fixed 133Mhz(66x2) Pentium II detected as 137Mhz ; (68.5x2). ;R88B 05/11/98 RAY Fixed some K5 CPU was detected as Cyrix MII ;R90 05/07/98 RCH Added 100x3.5=350Mhz support for AMD/K6/3D CPU. ;R52D 05/06/98 RCH Change CPU name display again for GXm and GXi ;R88A 05/04/98 RAY As requested by Cyrix: change MII display as "M II" ;R52C 04/27/98 MIL Added code to determine old MediaGX Part CPU. ;R89 04/25/98 RCH Added host clock 103 & 112Mhz support for 100Mhz ; platform and 68.5Mhz for 66Mhz platform to have ; correct CPU clock display ;R87A 04/24/98 RCH Update host clock table for P6 up to 133Mhz to ; support Katmai CPU. ;R88 04/23/98 RAY Add Cyrix MII CPU support with a new PR rating including ; clock multiplier 4x & 100Mhz bus clock ;R87 04/17/98 RCH Added Intel(R) new P2 CPU model (067X) support ;R83A 04/09/98 RCH Fixed system hang up for Pentium Pro platform due ; to reading CPU control register CTL3 ;R82A 04/08/98 RCH Change CELERON CPU name to "INTEL(R) CELERON(TM)" ; requested by Intel Taiwan. ;R86 04/03/98 RCH Changed M2 CPU Prating for 66/233 and 75/225 from ; PR266 to PR300 ;R85 03/31/98 RCH Rewrite frequency checking for x99Mhz to display ; (x+1)00Mhz instead for Penitum II CPUs ;R52B 03/23/98 MIL Added code to determine Cyrix "MediaGXi" or "MediaGXm" ; By CPU Register DIR1[7:4]. ;R84 03/17/98 RCH Program memory region C0000-C7FFFF to be WriteProtect ; if video ROM exist for P6 CPUs ;R83 03/16/98 RCH Re-write P2 MTRR programming method to support memory ; cacheable range over 512Mb for new PENTIUM II CPUs ; on both Single and Dual-processor platforms. ;R52A 03/13/98 RCH Change the display string of "MediaGX" to ; "Cyrix MediaGX". ;R82 03/12/98 RCH Show "CELERON" CPU name for Cavington (PENTIUM II ; without L2 cache) ;R81 03/12/98 RCH Fixed BIOS display 333Mhz if the host clock is 103Mhz ; and clock mode is x3.5 on jumperless platform ;R80 01/17/98 RCH Fixed boot to NT 3.51/SMP taking too long time when ; dual Pentium II are installed for MP platform ;R79 01/15/98 RCH Fixed wrong CPU clock display when CPU clock mode ; register is not match with real clock mode for old ; Pentium II CPUs. ;R78 12/17/97 RCH Added AMD-K6 3D CPU display , the CPU model is 058X. ;R77 11/25/97 DNL Add show For Intel Tillamook CPU ;R76 11/20/97 DRS Support M1 150Mhz(75*2) to report CPU75 ;R75 11/07/97 RAY Some chipset will hang up when accessing port 22/23 ; in the measuring speed routine. So we only access ; these ports if it is Cyrix CPU by checking CPU_BRAND[bp] ; which is ready in POST 09h ;R74 11/05/97 RCH Added ELAN/400 chipset support ;R73 11/04/97 RCH Added Unannounced Pentium/MMX CPU (058X) support ;R72 10/31/97 TNY Add "No_105MHz" for 2a59iz1c.cfg. ;R71A 10/27/97 RCH Don't turn ECC off if host clock is 100MHz for ; Pentium II & Deschutes CPUs ;R71 10/23/97 RCH Added Pentium II L2 cache ECC controlled by user ; CMOS setup. ;R70 10/13/97 RCH Fixed error coding for programming C6's ; "write combing". ;R69 10/03/97 RAY When M1 75x2, we should set CPU75 instead of CPU66 ;R68 09/26/97 RAY Add switch: Special_CPU_Clock_Table which make the BIOS ; do not reference the NewCPU_Int_Clock_Tbl. Instead, the ; BIOS that defined this switch should add a new table ; named "Ct_Int_Clock_Tbl" in the EGROUP segment of CHIPPOST.ASM ;R67 09/24/97 RAY Add switch: No_55MHz to support those customers that do ; not support 55MHz on their M/B ;R66 09/19/97 RCH Fixed Pentium Pro & P2 CPUs patch code not executed ; due to R156 of E0POST.ASM ;R65 09/18/97 RCH Change CPU name from "IDT-C6" to "IDT WinChip C6", ; requested by IDT. ;R64A 09/17/97 DRS R64 coding mistake cause M2 75x2 being shown as PR166 ; which should be shown as PR200 ;R64 09/13/97 DRS 1. Added M2 CPU auto core-to-bus clock ratio ; by referencing M2 register 0FEh which will reflect ; the clock ratio ; ; 2. Use new mothod to show P-Rating for M2 ; e.g. 66x2.5(166Mhz) show PR200 ; 83x2(166Mhz) show PR233 ; ;R63 09/10/97 RCH Added Deschutes CPU (065X) support for P6 class BIOS ;R62 09/08/97 TNY Add "Lower_233Mhz_FOR_ICS" definition ;R60A 08/26/97 RCH Added more models(058X & 059X) for K6 series CPUs ;R61 08/22/97 RCH Change the clock mode for 300Mhz from 60x5 to 66x4.5 ; for Pentium class CPUs. ;R46B 08/19/97 KVN Fixed the L2 cache of second Penitum Pro CPU always ; be disabled. ;R60 08/01/97 RCH Added AMD/K6 model 057X CPU ID(0.25 u) support ;R56B 07/30/97 RCH Fixed CPU_CLOCK not set properly in G_RAM for chipset ; reference. This bug cause the IDE timing can not ; set properly. ;R55C 07/28/97 RCH Cyrix request to show PR166 for 66x2 M2 CPU again. ;R59 07/24/97 TNY Fix IDT C6 hang up when install NT 4.0 ;R56A 07/22/97 TNY Fix some M/B detection error(300 MHz to be 299 MHz). ;R58 07/18/97 RCH The clock detection code already in shadow RAM(E-seg.) ; It is not necessary to copy into base memory for ; clock detection. ;R55B 07/17/97 RCH Show PR150 instead of PR166 for 66x2 M2 CPU ;R40B 07/15/97 MIL Fixed R40A coding mistake. ;R40A 07/12/97 MIL Fixed MediaGxi 166MHz CPU detect to 180MHz problem. ;R55A 07/11/97 RCH Show PR200 for M2 75x2 become standard. ;R57 07/11/97 KVN POST runtime decompress code compact to subroutine ;R56 07/11/97 RCH Re-write CPU detection algorithm for P6 class CPUs ; to get more accurate clock report ;R55 07/04/97 RCH Added special display for showing PR200 instead of ; PR166 for M2 for specific customers(requested by Cyrix) ;R53A 07/02/97 AVN Fixed SiS5596 for GEMLIGHT board still unstable, and ; added define 'Special_Align_for_M1_Clock_unstable' ; to save code for other chipset. ;R54 06/27/97 MIL Added some code for MediaGx CPU running over 133MHz. ;R53 06/27/97 AVN Fixed SiS5596 for GEMLIGHT board (2a5ifg3a) use CYRIX ; M1 CPU and clock set 60MHz/66MHz x 2 frequence and ; post detect cpu clock very unstable. ;R52 06/20/97 RAY Change the display string of Gx86 to "MediaGX" ;R50B 06/20/97 RCH Added "Write combining" for IDT-C6 CPU ;R50A 06/19/97 RCH Don't display "MMX" & "-S" for IDT-C6 CPU ;R51 06/19/97 RCH Added string "(tm)" display for AMD/K6 CPU ;R50 06/18/97 RCH Added IDT/C6 CPU support. BIOS treat this CPU as ; Pentium for CPU type that we don't need to modify ; all chipset dependent codes ;R45B 06/16/97 RCH Fixed system hang up if install DRAM over 512Mb and ; dual Penitum II CPUs are plugged. ;R46A 06/12/97 RCH Fixed the L2 cache of second Penitum II CPU always ; be disabled. ;R49 06/05/97 RAY Some customers do not want the BIOS the turn on the ; Write Allocation of the K5 CPU ;R48 06/02/97 RCH Many customers sale the PR133 AMD-K5 but the marking ; of CPU is PR150, added a switch to display it if ; customer need it.(SHOW_K5_PR150_INSTEAD_PR133) ;R47 05/29/97 KVN Added a new segment for store more BIOS code ;R46 05/29/97 RCH BIOS only disable first PPro/PII L2 cache if user ; disable L2 cache for MP platform. ;R45A 05/29/97 RCH Still set full cache address for onboard memory above ; 512Mb if L2 cache is disabled and using P II CPU ;R44A 05/26/97 RCH The L2 cache size is saved in MPINIT.ASM ;R45 05/21/97 RCH The L2 cacheable address range of current Pentium II ; is 512Mb(BBL_CT_CTL3[22:20]=000), BIOS need to set ; maximum cacheable range in CPU's MTRR to allow memory ; size usage above 512Mb. ;R44 05/21/97 RCH Fixed BIOS can not display L2 cache size of secondary ; Klamath CPU in MP system ;R43 05/20/97 RCH Added a item to separate "Video RAM" and "Video ROM" ; cacheability control for P6 system ;R42 05/19/97 TNY Add "NO_CPU_180MHZ_SUPPORT_FOR_ICS" definition. ;R39B 05/08/97 RCH Completed PR-rating table for Cyrix/M2 CPU ;R18D 05/02/97 RCH Change M2 CPU name from "M2" to "6x86MX", requested ; by IBM(R). ;R39A 04/25/97 RCH Fixed M2/188MHz can be displayed as PR233 ;R41 04/23/97 RAY Show "Gx86" instead of "Cx5x86" for Gx86 chip ;R40 04/23/97 RAY There are Cyrix GX86 CPUs that report a 3-time clock ; but in fact it is 4-time clock ;R39 04/21/97 RCH Temporary PR-rating display for M2. It's not final. ;R18C 04/21/97 LRY Removed showing Cyrix M2 the string '-MMX' ;R38 04/18/97 RCH Disable "bus pipeline" for K5 CPU with model 1,2 & 3 ; and stepping of 4 to get more stable operation ; Requested by AMD. ;R32C 04/18/97 RCH Changed CPU display for K6 from K6/PR2-XXX to K6/XXX ;R22B 03/27/97 LRY Define "CLOCK_TBL_FOR_ICS" for ICS clock generator ;R37 03/25/97 TNY Fix "CLOCK_TBL_FOR_ICWORK" 133 Mhz table. ;R36 03/17/97 TNY Add "Lower_150MHz_Tbl" definition. ;R26A 03/05/97 LRY Disable write cacheability detection not only for ; intel chipset, otherwise screen maybe have garbage ;R35 03/05/97 LRY For Cyrix M2 P200, fixed 2x & 2.5x CPU clock sizing ;R32B 02/27/97 RAY AMD change the K6 string to 'AMD-K6/PR2-XXX' where ; XXX is the core freq. ;R34 02/18/97 RAY Change the string "KLAMATH" to "PENTIUM II" as ; requested by Intel. ;R32A 02/21/97 RAY AMD insists the string 'AMD-K6/PRXXX' ;R33 02/17/97 TNY Enlarge intel 75MHz table. ;R32 02/17/97 RAY Support AMD's requests for K6 CPU: ; ; 1. Do not display 'MMX' on screen ; 2. Show P-rating according to the core freq. of ; the CPU ; ;R31 02/17/97 AVN For some motherboard use 68MHz clock for AMD K5 CPU ; BIOS show 150MHz, Now it will show 166MHz and no 60x2 ; clock support by define 'K586_68MHz_Show_133MHz' ;R29A 02/14/97 RCH The ALD/486 problem is caused by BOOTROM.ASM and it is ; fixed with R104D, so restore to original source. ;R22A 02/14/97 TNY Add ICWORK clock range. ;R25A 02/14/97 KVN Fixed no show full screen logo bug on 2M BIOS and you ; combine logo pattern at first area ;R30 02/13/97 RCH Some customers don't need 240Mhz support for Klamath ; due to high frequency output for specific clock ; generator. ;R29 01/31/97 RAY Fix ALD 486 chipset cannot dectect AMD DX4 CPU ;R28 01/27/97 RCH Cyrix request to display "PR" instead of "P" rating. ; same as AMD's CPU ;R27 01/24/97 RCH Move P6 USWC code for video display buffer from ; chippost.asm to kernel control. ;R18B 01/24/97 RCH Support M2 CPU for using INTEL flash and the boot ; block can not be flashed. ;R18A 01/24/97 RCH Support M2 CPU become standard feature ;R26 01/22/97 RAY Add Write Allocation support for K6 CPU ;R25 01/21/97 KVN Change MOV_SHAD_SEG value become 8000h to avoid conflit ; with POST runtiime decompress data ;R24 01/15/97 KVN Remove P6 micro code to ROM driver pool from 0E000h ; POST location ;R23 01/09/97 RCH Add support both Pentium Pro and Klamath CPUs in one ; BIOS. Note: It need 3 swtich in BIOS.CFG ; BOTH_P6_KLAMATH_CPU EQU 1 ; KLAMATH_CPU_ONLY EQU 1 ; P6_BIOS_ONLY EQU 1 ;R22 01/07/97 RCH ICWORKS clock generator's frequency is too slow, so ; create special table for clock judgement. ;R21 01/07/97 RCH Added 2nd CPU L2 cache initials. (Note: the code not ; test yet) ;R20 12/27/96 RCH Scan memory boundary from A31 to A16 due to 64Kb unit ; for POST memory scanning for P6 MTRR setting. ;R19 12/23/96 RCH Show PR200 for AMD-K5 133Mhz(only for CPUID 053X) ;R17B 12/20/96 RAY According to AMD's request: always enable the fix ; range(A0000-FFFFF) of the K5 write allocation. ; Bit set is disabling fix range's write allocation. ; this bit cleared will cause some PCI/VGA graphic ; display failure. ;R18 12/13/96 RCH Temporary support M2 CPU, This code must be modified ; after receiving sample. ;R17A 12/12/96 RCH Fixed error programming of AMD/K5 write allocation ; for memory hole from 15M-16M ;R13A 12/11/96 RAY The AMD K5's clock 50x1.75 entry should be ; placed after 60x1.5 entry to prevent system loading ; the 50Mhz setting when running on a 90Mhz Pentium. ;R10B 12/07/96 RAY Show 'MMX' for AMD K6 CPU ;R14A 12/07/96 RAY Re-define the input/ouput of routine Try_Show_PRating ; such that: ; ; 1. The screen will not mess up if there are CPUs ; in the future that we do not recgonize ; 2. Use word comparison for the CPU_INT_CLOCK[bp] ; instead of byte to prepare for future CPUs that ; may be having clock running over 255 MHz or ; having P-Rating over 255 ; ;R17 12/05/96 RAY Enable Write Allocation for AMD K5 CPUs ;R16 12/05/96 RAY Save codes by replacing "F000_CALL Get/Set_CMOS" ; with "call F000_Get/Set_CMOS" ;R10A 12/04/96 RAY More supports for AMD K6 in the following manners: ; ; 1. Show "AMD-K6" instead of "AMD-K5" for K6 CPU ; 2. Do not show P-rating in the current stage and ; will wait for AMD's further information. ; 3. K6 will have the same CPU type (in terms of value ; in CMOS 3Dh). All you have to do to differentiate ; K5 & K6 is to call a new public routine named ; "Check_K6_CPU" ; ;R15 12/04/96 RCH Added 187Mhz & 250Mhz table for future P5-class CPUs ;R14 12/03/96 RAY By AMD's request: ; ; Do not show the actual internal CPU clock for AMD ; & Cyrix CPU on screen by default. ; ; Add switch: DISP_MHZ_FOR_AMD_CYRIX to bypass the ; above default, i.e. always show internal clock ; ;R13 11/30/96 RAY Added AMD-K5 CPU with ID = 052xh & 053xh ;R12 11/30/96 RAY 1. Move all the CPU related code from E0POST.ASM & ; E8POST.ASM to here for easy debugging ; ; 2. Since there are codes should be linked to addr. ; between E8000-EFFFF, so add switch COMPILE_FOR_E0=0/1 ; in BIOS.MAK to compile this ASM file twice to ; generate CPUPOST.OBJ & CPUPE8.OBJ such that: ; ; CPUPOST.OBJ: linked before the fix ORG at E8000 ; CPUPE8.OBJ: linked after the fix ORG at E8000 ; ; 3. Change the assembler from 5.10A to 6.X ; ; ifdef MASM611 ; .MODEL SMALL, BASIC ; OPTION PROC: PRIVATE ; endif ;MASM611 ; ;R11 09/16/96 RCH Added Klamath CPUID(063x) support ;R10 07/29/96 RCH Added AMD-K6 CPU family ID support (056xh) ;R09 04/23/96 RCH Don't touch BTB if the CPU stepping is 051x or 052x ; due to extreme performance degraded for 0512H ; stepping. ;R08 04/05/96 RCH Public "Temp_Int06" for new CPU clock detection ; algorithm. ;R07 03/11/96 RCH Added CPU ID 163x for INTEL P6T CPU ;R06 03/04/96 RCH Fixed 100Mhz 6x86 CPU can not detected while update ; BIOS with INTEL boot block flash ( 28F001BX-T ) ;R05 01/24/96 RCH Added AMD/K5 CPU new family 051X support ;R04 01/18/96 RCH Disable CPU local APIC for P6 if it is not MP system ;R03 12/15/95 RAY Add CPU level information, i.e. 486, 586 or 686 ... ;R02 12/07/95 RAY Add X5 CPU information ;R01 11/30/95 RAY Since routine Temp_Int06 has moved to E000 segment, ; we should also fill the high word of the G_RAM:[int06] ; with E000h ! Otherwise, CPUs do not support CPUID ; instruction will hang up here ! ifdef MASM611 .MODEL SMALL, BASIC OPTION PROC: PRIVATE endif ;MASM611 .386p PAGE 60,132 TITLE CPU - CONTROL SPECIFIC CPU FUNCTIONS .XLIST INCLUDE BIOS.CFG INCLUDE COMMON.EQU INCLUDE POST.EQU INCLUDE CPU.EQU include 8259.equ include p6update.equ INCLUDE COMMON.MAC INCLUDE POST.MAC IF STR_function EQ 1 SM_RAM SEGMENT USE16 AT 0 INCLUDE SM_RAM.INC SM_RAM ENDS ENDIF ;STR_function EQ 1 G_RAM SEGMENT USE16 AT 0 ORG 04H*4 INCLUDE SEG_0.INC ORG 400H INCLUDE G_RAM.INC G_RAM ENDS ifdef VSA_VGA include CpuGx86.asm else ;VSA_VGA IF BIOS_SUPPORT_386 OR BIOS_SUPPORT_486 include Cpu3486.asm ENDIF ;BIOS_SUPPORT_386 OR BIOS_SUPPORT_486 IF BIOS_SUPPORT_586 include Cpu586.asm ENDIF ;BIOS_SUPPORT_386 IF BIOS_SUPPORT_686 include Cpu686.asm ENDIF ;BIOS_SUPPORT_686 endif ;VSA_VGA DGROUP GROUP FCODE FCODE SEGMENT PARA PUBLIC 'CODE' ASSUME CS:DGROUP FCODE ENDS END