; []===========================================================[] ; ; NOTICE: THIS PROGRAM BELONGS TO AWARD SOFTWARE INTERNATIONAL(R) ; INC. IT IS CONSIDERED A TRADE SECRET AND IS NOT TO BE ; DIVULGED OR USED BY PARTIES WHO HAVE NOT RECEIVED ; WRITTEN AUTHORIZATION FROM THE OWNER. ; ; []===========================================================[] ; ;---------------------------------------------------------------------------- ;Rev Date Name Description ;---------------------------------------------------------------------------- ;R51 05/02/99 ADS Add "GPO_LOW_IF_VIDEO_OK" and "GPO_LOW_IF_MEMORY_OK" ; option for customer requset. ;R50 04/29/99 RIC Add "X_If_693A" routine and ; public "X_Measure_SDRAM_Speed" routine. ;R49 04/23/99 RAX Added code to patch 3COM Lan card can't enter low power ; state and under Win98 APM mode can't work when reset on ; "even" times. ;R47B 04/22/99 RIC "VIA_Y2K_Patch" definition can be used in 596B chip. ;R18A 04/20/99 ADS Fix that the IRQ of SCI assign fail in ; new VIA Super SouthBridge VT686. ;R47A 04/08/99 RIC Add "VIA_Y2K_Patch" definition for R47 code for ; temporal because it function have some problem. ;R48A 04/08/99 RCH Support external IOAPIC for MP platform ;R48 04/02/99 RCH Added support for Multi-Processor platform ;R47 04/01/99 RIC Add Patch Y2K CMOS 32h function. ;R46A 03/30/99 RIC Fixed that compile error in "No_Suggested_SDRAM_CL" ; definition ;R14A 03/25/99 RIC Fixed that compile error in no "SMBus_Port" definition. ;R46 03/24/99 RIC Add show DRAM_Clock_Error_String function ; and "No_Suggested_DRAM_Clock" definition. ;R45 03/16/99 RIC Fixed that Resume Item auto-hide fail in 596/686A chip. ;R44A 03/11/99 RAX Added define removal menuitem. ;R44 03/10/99 RIC Support 693A DRAM Asynchronous. ;R43 03/04/99 RIC Don't let the IRQ of Sound Blaster share to other ; Device because this Sound Blaster is Legacy ISA. ;R42 02/26/98 RIC Fix that UltraDMA 66 CLK don't be open when UltraDMA ; 66 pluged. ;R41 02/24/99 RIC Enable AC-Link Variable-Sample-Rate(AC97 Rx41<3>=1) ;R40 02/11/99 RIC Fix that Hareware RESET cause syetm auto-PowerOff when ; Power Fail item set 'OFF'. ; If you don't want to cover it. ; You want to the same as PIIX4, please define: ; "PowerFail_As_PIIX4 EQU 1" ;R39 02/11/99 RIC Protect RTC 0Dh write for new 686A chip. ;R31A 02/09/99 ADS Fixe complier error. ;R38 02/05/99 RIC Latency Time of NorthBridge set to 00h for speeding up ; UltraDMA 66 performance. ;R37 01/29/99 PAL Move "SndChip_Cntl_USE_ClkGen" to CLKCNTL.ASM ;R36 01/26/99 RAX Added PCI slot master control for customer. ;R35 01/19/99 RIC Fixed that compile fail(out of memory) in pnp.equ of ; chippost.asm ;R34 01/06/99 RIC Add "SHOW_ECC_FUNC" definition for ECC status show. ;R33 01/05/99 ADS Add "Issue_Gemlight_TV_Out_Function" define for customer request. ;R32 12/28/98 RIC Modify the CMOS index of the flag of exit form SETUP ; (F0h => F4h) ;R25A 12/21/98 RIC Fix that system screen show blank in Win95 shatdown ; when BIOS Cacheable is enabled. ;R31 12/21/98 RIC Add "USB2_Separate_Control" define. ;R30 12/21/98 RIC Support UltraDMA66 HDD in 686/686A SouthBridge. ; You must define the cable detection Pin of CH1/CH2 ; UltraDMA66 : ; CH1_UltraDMA66_High_In_GPI EQU 1....13 ; CH1_UltraDMA66_Low_In_GPI EQU 1....13 ; CH2_UltraDMA66_High_In_GPI EQU 1....13 ; CH2_UltraDMA66_Low_In_GPI EQU 1....13 ; (example) ; CH1_UltraDMA66_Low_In_GPI EQU 1 ;GPI1 Low mean => CH1 Ultra66 ; CH2_UltraDMA66_Low_In_GPI EQU 3 ;GPI3 Low mean => CH2 Ultra66 ; ;R29 12/15/98 RIC Don't destroy the value of CX in _Set_Ct/X_Set_Ct routine. ;R28 12/11/98 RIC Add code to control second USB controller On/Off. ;R27A 12/10/98 PAL Fixed R27 coding error jmp segment call hook method error ;R27 11/27/98 PAL Add "SndChip_Cntl_USE_ClkGen" option ;R26 11/24/98 RIC Add "HALT_IF_VGA_NOT_FOUND" option. (This option ; will be with bug if MONO card plugged only) ;R25 11/19/98 RIC Add BiosCache_Item feature. ;R24 11/17/98 RIC Add "GPO_LOW_BEFORE_BOOT" ; "GPO_HIGH_BEFORE_BOOT" definition. ;R23 11/16/98 RIC Fix that exit from setup auto-PowerOff when Power Fail ; Item set 'Off'. ;R22 11/16/98 RIC Fix that Trend Anti-Virus replace F0000-F4800 area. ; So move Get_Set_Ct_OR, Get_Set_Ct_AND to chiprun. ;R21 11/13/98 PAL Remove E000 shadow control code to PMUPOST.ASM ; to avoid Trend code destroy ;R20 11/05/98 RIC Add "VIA686HM_SUPPORT" definition. ;R19 11/03/98 RIC Add "GPO_HIGH_BEFORE_BOOT","GPO_LOW_BEFORE_BOOT" define. ;R18 10/26/98 RIC Fix that the IRQ of SCI assign fail in ; new VIA Super SouthBridge VT686. ;R17 10/21/98 RIC Enable 'Clear DMA Write Flag by IO Write to Port 1F7h/177h' ; function of IDE of 596 chip. ; (Fix that OPTI Audio Card have garbage in W95/98) ;R13A 10/19/98 RIC Fix that R13 code cause system hang at PCI RESET ; in ITE8671 IO chip. ;R16 10/14/98 RIC Disable IDE PreFetch when IDE CDROM used. ;R15 10/12/98 RIC Add "CAS_Latency_Auto" function. ;R04A 10/09/98 RIC If VT596 is new version , Don't perform ; "UltraMode2_No_Set_Mode1" function. ;R14 10/07/98 PAL Added I2C access code for all SMbus ;R13 10/06/98 RIC Fix that Garbage IRQ12 of SuperIO cause system can't ; entry Suspend when no PS2 mouse pluged. ;R12 10/02/98 RIC Add the function that SDRAM run saft timing when ; system power on three times fail. ;R11 10/02/98 BAR Fixed define support " No_Support_4_IDE " ; compile error. ;R05A 09/30/98 RIC Modify "DRAM_Bank_Show_As_SIMM" show algorithm ;R10 09/23/98 RIC Change ACPI IRQ assign algorithm to Auto-assigned. ; If you want to use old algorithm, please define: ; 1."No_ACPI_IRQ_Auto_Assign" for disabled new algorithm. ; 2."ACPI_IRQ_Selectable" for enabled old algorithm. ;R09 09/22/98 RIC Fix that WOL hang in POST 0Dh in some mainboard ; (with 596 SouthBridge) ;R08 09/15/98 RIC Change the default of DRAM Timing Item to SDRAM. ;R07A 09/15/98 RIC Modify algorithm and change definition to ; "No_Suggested_SDRAM_CL" from "CAS_Latency_Error_String" ;R07 09/14/98 RIC Add "CAS_Latency_Error_String" define to show message ; for SDRAM don't support CAS Latency 2T or not support SPD. ;R06 09/14/98 RIC Add 'KcMoS' sign for CKCMOS. ;R05 09/11/98 RIC Add "DRAM_Bank_Show_As_SIMM" define. ;R04 09/08/98 RIC Re-write E000_IDE_Special_Do.(old file copy to *.908) ;R03 09/04/98 RIC Fix that new 596 version fail in PCI2.1 Card of HCT7.6. ;R02 09/02/98 RIC Fix that compile error in no USB case. ;R01 09/01/98 RIC Add "OEM1_GPO_CNTL" define. ; "OEM2_GPO_CNTL" ; "OEM3_GPO_CNTL" ;R00 08/24/98 RIC Initialization. .386p PAGE 56,132 TITLE CHIPSET -- 386/486 EISA ROM/BIOS ;---------------; ; Include ; ;---------------; INCLUDE BIOS.CFG INCLUDE POST.EQU INCLUDE COMMON.MAC INCLUDE POST.MAC ;R48 include CPU.EQU ;R48 include CT_TABLE.EQU ;R35 ifdef PNP_BIOS ;R35 include pnp.equ ;R35 endif; PNP_BIOS ifdef PNP_BIOS ;R43 include pnp.equ ;R43 endif; PNP_BIOS ;R43 INCLUDE CHIPSET.EQU ;-----------------------; ; External Subroutine ; ;-----------------------; ;***************; ; Kernel ; ;***************; extrn Get_Cmos:near extrn Set_Cmos:near extrn GetItem_Value:Near extrn F000_Getitem_Value:near extrn X_GetItem_Value:Near extrn GetItem_Cmos:Near extrn XCALL_PROC:near extrn Post_call_proc:near extrn F000_call_proc:near extrn F000_Display_String:near extrn X_Display_String:near extrn Pci_IO_Mem_Init:near extrn F000_Shadow_W:near extrn F000_Shadow_R:near ifdef PCI_BUS extrn AGet_CfgSpace_Word:near ;PCI1A.ASM extrn AGet_CfgSpace_BYTE:near ;PCI1A.ASM extrn ASet_CfgSpace_BYTE:near ;PCI1A.ASM extrn AGet_CfgSpace_DWord:near ;PCI1A.ASM extrn ASet_CfgSpace_DWord:near ;PCI1A.ASM ;R49 start extrn F000_Get_CfgSpace_Word:near extrn F000_Set_CfgSpace_Word:near extrn F000_Get_CfgSpace_DWord:near extrn F000_Set_CfgSpace_DWord:near ;R49 end endif; PCI_BUS ifdef VIA686AIO ;R43 extrn Sound_Blaster_Item:near ;R43 extrn SB_IRQ_Item:near ;R43 endif; VIA686AIO ;R43 ;***************; ; Chipset ; ;***************; extrn Get_Ct:near extrn Set_Ct:near extrn Get_Set_Ct:near extrn Get_Set_Ct_OR:near ;R22 extrn Get_Set_Ct_AND:near ;R22 extrn Get_Set_PMU_OR:near ;R22 extrn Get_Set_PMU_AND:near ;R22 extrn Get_PMIO:near extrn Set_PMIO:near extrn Get_Set_PMIO:near extrn Get_Set_PMIO_OR:near extrn Get_Set_PMIO_AND:near extrn E000_Get_PMIO:near extrn E000_Set_PMIO:near extrn E000_Get_Set_PMIO_OR:near extrn E000_Get_Set_PMIO:near extrn E000_Get_Set_PMIO_OR:near extrn E000_Get_Set_PMIO_AND:near ifdef Have_BankInterleave_Item IFDEF Have_Page_Mode_Item extrn Test_DRAM:near ENDIF;Have_Page_Mode_Item endif; Have_BankInterleave_Item extrn X_If_100MHz_DRAM_Clock:Near extrn E000_GPO_Pin_Low:near ;R19 extrn E000_GPO_Pin_High:near ;R19 extrn E000_Read_GPI_Pin:Near ;R30 ;-----------------------; ; External Item/Label ; ;-----------------------; ;***************; ; Kernel ; ;***************; ifdef ACPI_Support ifdef Special_ACPI_Table_Update include acpi.inc extrn FACP_Pointer:near endif; Special_ACPI_Table_Update endif; ACPI_Support ;***************; ; Chipset ; ;***************; ; Chipset FEAT extrn SDRAM_CL_Item:Near extrn Delay_Trans_Item:near extrn Mem_Hole_Item:near ;R25 extrn VideoCache_Item:near extrn BiosCache_Item:near ;R25 ifdef Have_BankInterleave_Item extrn SDRAM_BK_Item:Near endif; Have_BankInterleave_Item ;R33 - starts ifdef Issue_Gemlight_TV_Out_Function extrn TV_Out_Mode_Item:near endif; Issue_Gemlight_TV_Out_Function ;R33 - ends ifdef Have_Page_Mode_Item extrn DRAM_Page_Mode_Item:Near endif; Have_Page_Mode_Item ifdef Have_AGP_Item extrn AGP_Item:near endif; Have_AGP_Item extrn Aperture_Size_Item:near ifdef VT586_USB ;R02 extrn ONBD_USB_Item:Near endif ;VT586_USB ;R02 ;R02ifdef VT586_USB ;R02 extrn USB_Legacy_Item:near ;R02endif ;VT586_USB extrn Bank01_Dram_Timing_Val:Near extrn Bank01_Dram_Timing_Val_:Near extrn Bank23_Dram_Timing_Val:Near extrn Bank23_Dram_Timing_Val_:Near extrn Bank45_Dram_Timing_Val:Near extrn Bank45_Dram_Timing_Val_:Near extrn Bank67_Dram_Timing_Val:Near extrn Bank67_Dram_Timing_Val_:Near extrn UltraMode2_Set_Mode1_Status:Near ifdef USB2_Separate_Control ;R31 - starts extrn ONBD_USB_2_Item:Near endif; USB2_Separate_Control ;R31 - ends ifndef No_Have_DRAM_Async_Item ;R44A extrn DRAM_Async_Val_:Near ;R44 endif ;No_Have_DRAM_Async_Item ;R44A ; PNP FEAT ifdef ACPI_Support extrn ACPI_option_Item:Near ;R10 IFNDEF No_ACPI_IRQ_Selectable IFDEF ACPI_IRQ_Selectable ;R10 extrn Assign_ACPI_IRQ_Item:Near ;R10 ENDIF; No_ACPI_IRQ_Selectable ENDIF;ACPI_IRQ_Selectable ;R10 endif; ACPI_Support ; PCI FEAT ;R36 start ifdef PCISLOT_MASTER_CONTROL extrn PCI_CONFIG1_Item:near extrn PCI_CONFIG2_Item:near extrn PCI_CONFIG3_Item:near endif ;PCISLOT_MASTER_CONTROL ;R36 end ; PM FEAT ifndef No_Auto_Hidden_Resume_Item IFNDEF Always_ATX_Power ifdef Have_Keyboard_PowerOn_Item extrn KB_Item:Near endif; Have_Keyboard_PowerOn_Item IFNDEF VT596 ifdef Wake_On_EXTSMI0_Support extrn WO_Item:Near endif; Wake_On_EXTSMI0_Support ENDIF; VT596 extrn Ring_Item:Near extrn Alarm_Item:Near extrn Alarm_Timer_Date_Item:Near extrn Alarm_Timer_Hour_Item:Near extrn Alarm_Timer_Min_Item:Near extrn Alarm_Timer_Sec_Item:Near ENDIF; Always_ATX_Power endif; No_Auto_Hidden_Resume_Item ; IO FEAT extrn IDE_PF_Item:near ifdef PCI_BUS extrn ONBD_1IDE_Item:near extrn ONBD_2IDE_Item:near endif; PCI_BUS ifdef NEW_IDE_MODE_3 extrn IdeA_Mode_Item:near extrn IdeB_Mode_Item:near IFNDEF ONCHIP_2ND_ALWAYS_DISABLE ifdef Support_4_IDE ;R11 extrn IdeC_Mode_Item:near extrn IdeD_Mode_Item:near endif; Support_4_IDE ;R11 ENDIF; ONCHIP_2ND_ALWAYS_DISABLE IFDEF Have_IDE_Threshold_Item extrn IDE_Threshold_Item:near ENDIF; Have_IDE_Threshold_Item endif; NEW_IDE_MODE_3 ifndef VT596 IFDEF Control_Onchip_By_GPIO_Low extrn ONBD_Chip_Item:near ENDIF;Control_Onchip_By_GPIO_Low else; VT596 IFDEF Control_Onchip_By_GPO_Low extrn ONBD_Chip_Item:near ENDIF;Control_Onchip_By_GPO_Low IFDEF Control_Onchip_By_GPO_High extrn ONBD_Chip_Item:near ENDIF;Control_Onchip_By_GPO_High endif; VT596 ;R27 - start ;R37ifdef SndChip_Cntl_USE_ClkGen ;R37 extrn E000_64K_shadow_R:near ;R37endif; SndChip_Cntl_USE_ClkGen ;R27 - end G_RAM SEGMENT USE16 AT 0 ORG 04H*4 INCLUDE SEG_0.INC ORG 400H INCLUDE G_RAM.INC ifdef PNP_BIOS ;R43 ORG 2000h ;R43 INCLUDE PNPDATA.INC ;R43 endif ;PNP_BIOS ;R43 G_RAM ENDS DGROUP GROUP FCODE DGROUP GROUP FCODE FCODE SEGMENT USE16 PARA PUBLIC 'CODE' ASSUME CS:DGROUP,DS:DGROUP ifndef COMPRESS_CODE include chipboot.asm endif ;COMPRESS_CODE ;[]==============================================================[] ; ; Enable_Linear_Burst: (POST 09h) (CPUPOST.asm INIT_CYRIX ) ; ; Turn on chipset linear burst function to support Cyrix M1 CPU ; ; Saves: SP ; Entry: None ; Exit: Cy = 0 Support Linear Burst Function ; Cy = 1 No Support Linear Burst Function ; Note : 1. Stack Available ;[]==============================================================[] Public Enable_Linear_Burst Enable_Linear_Burst Proc Near stc ; No Linear Burst Support ret Enable_Linear_Burst Endp ;[]==============================================================[] ; ; Ct_Early_Shadow: (POST 0Bh) ; ; Shadowing system and video BIOS to speedup booting. ; ;Saves: ; ; All except ax,dx,es,ds,flag ;Input : None ;Output: None ; ;[Notes] ; ; 1. This routine will shadow system BIOS in early stage ; of POST. ; 2. Stack available ;[]==============================================================[] align 4 public Ct_Early_Shadow Ct_Early_Shadow proc near ifdef PCI_BUS call far ptr E000_Ct_Early_Shadow ;Docket is IDE/AGP/other Device initialize call Pci_IO_Mem_Init endif; PCI_BUS call far ptr E000_Ct_Early_Shadow_1 ;R51 - start ifdef GPO_LOW_IF_VIDEO_OK push es mov ax, 0C000h mov es, ax cmp word ptr es:[0],0AA55h jne short VideoFail mov bl, GPO_LOW_IF_VIDEO_OK post_func_call E000_GPO_Pin_Low ;low for on VideoFail: pop es endif; GPO_LOW_IF_VIDEO_OK ifdef GPO_LOW_IF_MEMORY_OK mov bl, GPO_LOW_IF_MEMORY_OK post_func_call E000_GPO_Pin_Low ;low for on endif; GPO_LOW_IF_MEMORY_OK ;R51 - end ret Ct_Early_Shadow ENDP ;[]==============================================================[] ;CACHE_INIT: (POST 09h) ; Cache controller initialization after first testing ; first 64k memory. ;Saves: ALL but flags ;Input: none ;Output:none ; ;[Notes] 1. Stack is available ; 2. This function can be used to sizing cache size ;[]==============================================================[] align 4 public Cache_Init Cache_Init proc near call far ptr X_Cache_Init ;Docket is PCI IRQ initialize ;R48 - start ifdef MP_SUPPORT extrn Cpu_Apic_Init:near call Cpu_Apic_Init endif; MP_SUPPORT ;R48 - end clc ret Cache_Init endp ;[]==============================================================[] ;Ct_Parity_Control: (POST 52h) ; Programming chipset registers of memory parity check ;Saves: all but flags ;Input: AL - 0 = disable parity check ; - 1 = enable parity check ;Output:none ; ;[Notes] 1. Stack and BP is available ; 2. This function can be used to program special chipset ; registers about memory parity check ;[]==============================================================[] public Ct_Parity_Control Ct_Parity_Control proc near ret ; Dummy Return Ct_Parity_Control endp ;[]==============================================================[] ;CT_FINAL_INIT: (POST 61h) ; Programming chipset registers before boot ;Saves: all but flags ;Input: none ;Output:none ; ;[Notes] 1. Stack and BP is available ; 2. This function can be used to program special chipset ; registers before boot ;[]==============================================================[] public CT_FINAL_INIT CT_FINAL_INIT proc near call far ptr X_ct_final_init ret CT_FINAL_INIT endp ;[]==============================================================[] ;Get_Cache_Size: (POST 61h) ; Return chipset cache size to display ;Input : None ;Output: AL - 0 = 0K, 1=16K , 2=32K , 3=64K , 4=128K , 5=256K ; 6 =512K, 7=1024K ,etc... ;[]==============================================================[] PUBLIC Get_Cache_Size Get_Cache_Size PROC NEAR ret ; Dummy Return Get_Cache_Size ENDP ;[]==============================================================[] ;GET_CPU_SPEED: (POST 0Dh) ; Program some chipset registers according to CPU clock ; in G_RAM:CPU_CLOCK ;Saves: all but flags ;Input: none ;Output:none ; ;[Notes] 1. Stack and BP is available ; 2. You can program AT bus clock to about 8Mhz according ; to cpu clock ;[]==============================================================[] PUBLIC Get_CPU_Speed Get_Cpu_Speed proc near ret ; Dummy Return Get_Cpu_Speed endp ;[]==============================================================[] ;CT_REMAP: (POST 30h) ; Remap unused memory from 640k to 1M ;Saves: all but flags ;Input: none ;Output:none ;[Notes] 1. Program chipset register if remap allowed. ;[]==============================================================[] public Ct_Remap Ct_Remap proc near call far ptr E000_Ct_Remap ;R07A ;R07 - starts ;R07A ifdef CAS_Latency_Error_String ;R07A call far ptr X_CAS_Latency_Error_String ;R07A endif; CAS_Latency_Error_String ;R07A ;R07 - ends ret Ct_Remap endp ;[]==============================================================[] ;Ct_Disable_Onboard_Vga: (Reserved) ; Disable onboard C000H video ROM by setting chipset register ; Input : None ; Output: None ; Save: all ; [Note]: 1. This is used to auto-detect onboard C0000H video ROM ; and video ROM on slot. ;[]==============================================================[] public Ct_Disable_Onboard_Vga Ct_Disable_Onboard_Vga proc near ret Ct_Disable_Onboard_Vga endp ;[]==============================================================[] ;Ct_Enable_Onboard_Vga (Reserved) ; Enable onboard C000H video ROM by setting chipset register ; Input : None ; Output: None ; Save: all ; [Note]: 1. This is used to auto-detect onboard C0000H video ROM ; and video ROM on slot. ;[]==============================================================[] public Ct_Enable_Onboard_Vga Ct_Enable_Onboard_Vga proc near ret Ct_Enable_Onboard_Vga endp ;[]==============================================================[] ;Ct_Disable_E000_Vga: (Reserved) ; Disable onboard E000H video ROM by setting chipset register ; Input : None ; Output: None ; Save: all ; [Note]: 1. This is used to auto-detect onboard E0000H video ROM ; and video ROM on slot. ;[]==============================================================[] public Ct_Disable_E000_Vga Ct_Disable_E000_Vga proc near ret Ct_Disable_E000_Vga endp ;[]==============================================================[] ;Ct_Enable_E000_Vga: (Reserved) ; Enable onboard E000H video ROM by setting chipset register ; Input : None ; Output: None ; Save: all ; [Note]: 1. This is used to auto-detect onboard E0000H video ROM ; and video ROM on slot. ;[]==============================================================[] public Ct_Enable_E000_Vga Ct_Enable_E000_Vga proc near ret Ct_Enable_E000_Vga endp ;[]==============================================================[] ;Ct_Check_System_Shadow: (Reserved) ; Check sytem BIOS is shadowed or not. ; Input : None ; Output: flag zero set - System BIOS is shadowed ; zero clear - System BIOS is not shadowed ; Save: all except ax ; [Note]: 1. This is used to fix NOVELL problem on user-defined ; hard disk. ; 2. You must return real status of system shadow, ; otherwise may boot fail on HDD. ;[]==============================================================[] public Ct_Check_System_Shadow Ct_Check_System_Shadow proc near ret Ct_Check_System_Shadow endp ;[]==============================================================[] ; Ct_Init_Cyrix : (POST 09h) (CPUPOST.asm INIT_CYRIX ) ; Program chipset register for CYRIX CPU ; Input : None ; Output: None ; Save: all ; [Note]: 1. Just return if chipset did not need programming ;[]==============================================================[] public Ct_Init_Cyrix Ct_Init_Cyrix proc near ret ; Dummy Return Ct_Init_Cyrix endp ;R21;[]==============================================================[] ;R21; Disable_E000_ROM_Shadow : (POST 63h) ;R21; Disable E000 ROM Shadow (Direct Access to ISA) ;R21; Input : None ;R21; Output: None ;R21; Save: all ;R21;[]==============================================================[] ;R21 public Disable_E000_ROM_Shadow ;R21Disable_E000_ROM_Shadow proc near ;R21 ;R21 ;disable E0000 shadow RAM ;R21 ;R21 mov cx,VT692 + 63h ;R21 mov bl,NOT 0c0H ;R21 call Get_Set_Ct_AND ;R21 ;R21 ;disable onboard E0000 ROM ;R21 mov cx,VT586 + 43h ;R21 mov bl,NOT 30H ;R21 call Get_Set_Ct_AND ;R21 ;R21 ret ;R21Disable_E000_ROM_Shadow endp ;[]==============================================================[] ;Check C0000-EFFFF shadow allowed or not (POST 0Eh) ; Some chipset's shadow is dependent on F0000 shadowing, i.e. ; If F0000 was not shadowed, all other segment of ROM can't be ; shadowed. ;Input : none ;Output: zero set - shadow allow ; zero not set - shdow not allow ;[]==============================================================[] public Ct_Shadow_Alone_Check Ct_Shadow_Alone_Check proc near ifndef No_SDRAM_Load_Default ;R12 - starts IFDEF Clear_SDRAM_Load_D4_In_POST0E ;-----------------------------------------------; ; Reset the Status of SDRAM_Load_Default ; ;-----------------------------------------------; IFNDEF SDRAM_Load_Default_CMOS mov al, [bp]+ 37h and al, not (03h) or al, ((03h shl 1) and (03h)) mov [bp]+37h, al ELSE; SDRAM_Load_Default_CMOS mov al, [bp]+ SDRAM_Load_Default_CMOS and al, not (SDRAM_Load_Default_Bit) or al, ((SDRAM_Load_Default_Bit shl 1) and (SDRAM_Load_Default_Bit)) mov [bp]+SDRAM_Load_Default_CMOS, al ENDIF; SDRAM_Load_Default_CMOS ENDIF;Clear_SDRAM_Load_D4_In_POST0E endif ;No_SDRAM_Load_Default ;R12 - ends xor al,al ret Ct_Shadow_Alone_Check endp ;[]==============================================================[] ;C000_Shadow_RW: ; Set video BIOS(C000-C800) shadow enable & writeable ;Input : none ;Output: none ;[]==============================================================[] public C000_Shadow_RW C000_Shadow_RW proc near mov cx,VT692 + 61h mov bx,0ff0h call GET_SET_CT ret C000_Shadow_RW endp ;[]==============================================================[] ;C000_Shadow_R: ; Set video BIOS(C000-C800) shadow readonly ;Input : none ;Output: none ;[]==============================================================[] public C000_Shadow_R C000_Shadow_R proc near mov cx,VT692 + 61h mov bx,0af0h call GET_SET_CT ret C000_Shadow_R endp ;[]==============================================================[] ;E000_Shadow_W: ; Set video BIOS(E000-E800) shadow enable & writeable ;Input : none ;Output: none ;[]==============================================================[] public E000_Shadow_W E000_Shadow_W proc near mov cx,VT692 + 63h mov bx,403fh call GET_SET_CT ret E000_Shadow_W endp ;R21;[]==============================================================[] ;R21;E000_Shadow_R: ;R21; Set video BIOS(E000-E800) shadow readonly ;R21;Input : none ;R21;Output: none ;R21;[]==============================================================[] ;R21 public E000_Shadow_R ;R21E000_Shadow_R proc near ;R21 mov cx,VT692 + 63h ;R21 mov bx,803fh ;R21 call GET_SET_CT ;R21 ret ;R21E000_Shadow_R endp ;[]==============================================================[] ;C800_Shadow: (Reserve) ; Shadow adaptor ROM C8000-CBFFF ;CC00_Shadow: (Reserve) ; Shadow adaptor ROM CC000-CFFFF ;D000_Shadow: (Reserve) ; Shadow adaptor ROM D0000-D3FFF ;D400_Shadow: (Reserve) ; Shadow adaptor ROM D4000-D7FFF ;D800_Shadow: (Reserve) ; Shadow adaptor ROM D8000-DBFFF ;DC00_Shadow: (Reserve) ; Shadow adaptor ROM DC000-DFFFF ;E000_Shadow: (Reserve) ; Shadow adaptor ROM E0000-E3FFF ;E400_Shadow: (Reserve) ; Shadow adaptor ROM E4000-E7FFF ;E800_Shadow: (Reserve) ; Shadow adaptor ROM E8000-EBFFF ;EC00_Shadow: (Reserve) ; Shadow adaptor ROM EC000-EFFFF ;Input : none ;Output: none ;[]==============================================================[] public C800_Shadow public CC00_Shadow public D000_Shadow public D400_Shadow public D800_Shadow public DC00_Shadow public E000_Shadow public E400_Shadow public E800_Shadow public EC00_Shadow C800_Shadow proc near CC00_Shadow: D000_Shadow: D400_Shadow: D800_Shadow: DC00_Shadow: E000_Shadow: E400_Shadow: E800_Shadow: EC00_Shadow: ret C800_Shadow endp Public E000_64K_shadow_RW E000_64K_shadow_RW Proc Near mov cx,VT692 + 63h mov bx,0C03fh call GET_SET_CT ret E000_64K_shadow_RW Endp ;R21 Public E000_64K_shadow_R ;R21E000_64K_shadow_R Proc Near ;R21 jmp E000_Shadow_R ;R21E000_64K_shadow_R Endp ;[]==============================================================[] ;Set_High_Speed: (POST 0Dh) ; Set system to high speed before CPU clock detecting ; during POST ;Input : none ;Output: none ;[]==============================================================[] Public Set_High_Speed Set_High_Speed Proc Near ;R26 - start ifdef HALT_IF_VGA_NOT_FOUND call far ptr Halt_System_IF_NOVGA endif; HALT_IF_VGA_NOT_FOUND ;R26 - end ret Set_High_Speed Endp ;[]==============================================================[] ;Restore_Speed: (POST 0Dh) ; Restore system speed after CPU clock detecting set by ; Set_High_Speed routine during POST if needed ;Input : none ;Output: none ;[]==============================================================[] Public Restore_Speed Restore_Speed Proc Near ret Restore_Speed Endp ;[]==============================================================[] ;Init_Onboard_Io: (POST 32h) ; Initial onboard I/O chip ;Save : all but flags ;Input : none ;Output: none ;Note : 1. This routine will be called before I/O installation. ; 2. This is a customerization routine if you need. ;[]==============================================================[] public Init_Onboard_Io Init_Onboard_Io proc near call far ptr X_Init_Onboard_Io ;R07A - starts IFDEF SMBus_Port ;R46 ifndef No_Suggested_SDRAM_CL call far ptr X_CAS_Latency_Error_String endif; No_Suggested_SDRAM_CL ifndef No_Suggested_DRAM_Clock ;R46 call far ptr X_DRAM_Clock_Error_String ;R46 endif; No_Suggested_DRAM_Clock ;R46 ENDIF; SMBus_Port ;R46 ;R07A - ends ret Init_Onboard_Io endp ;[]==============================================================[] ;Ct_Before_Setup: (Before SETUP) ; Program some improper registers if problem occured when ; entering setup ;Save : all but flags ;Input : none ;Output: none ;Note : 1. This routine will be called before entering setup ; 2. Some chipset will hang or improper operation while ; entering setup. ;[]==============================================================[] public Ct_Before_Setup Ct_Before_Setup proc near ifdef Record_PWRON_Status IFDEF PowerFail_As_PIIX4 ;R40 ;R32 mov al,0F0h ; Save Flag of Entry SETUP. mov al,0F4h ;R32 Save Flag of Entry SETUP. out 72h,al ; mov al,0A5h ; out 73h,al ; ENDIF;PowerFail_As_PIIX4 ;R40 endif; Record_PWRON_Status ret Ct_Before_Setup endp ;[]==============================================================[] ;Ct_Auto_Check: (POST 41h) ; Check if program chipset registers with AUTO table or not ;Save : all but flags ;Input : none ;Output: zero flag set - No auto-config. ; zero flag clear - Program with AUTO table ;Note : 1. This routine will be called before auto-programming ; 2. You must read setup value (according setup item ) ; to judge auto-programming is allowed or not. and return ; correct zero flag. ;[]==============================================================[] public Ct_Auto_Check Ct_Auto_Check proc near or al,1 ; Clear zero flag ret Ct_Auto_Check endp ;[]==============================================================[] ;Ct_Shadow_Allow: (Reserved) ; Check if any shadow RAM available ;Save : all but flags ;Input : none ;Output: zero flag set - shadow RAM available ; zero flag clear - No shadow RAM ;Note : 1. This routine will be called before shadowing ; 2. You must return non-zero flag if your system have no ; shadow RAMs or total memory is 512k only ;[]==============================================================[] public Ct_Shadow_Allow Ct_Shadow_Allow proc near xor al,al ;shadow RAM available ret Ct_Shadow_Allow endp ;[]==============================================================[] ;Ct_Ext_Mem_Limit: (POST 30h) ; Limit maximum memory size according to onboard DRAM ;Save : all but flags ;Input : AX - No. of 1k memory size ;Output: AX - max. No. of 1m memory size return ;Note : 1. This routine will be called after memory sizing ; 2. This routine is optional , because our BIOS can not ; detect memory size for some special chipset. ; For example : actual memory size is 16384 Kb , Our BIOS ; detect it as 64512 Kb , and I known it is ; real 16384 Kb only. ;[]==============================================================[] public Ct_Ext_Mem_Limit Ct_Ext_Mem_Limit proc near ret Ct_Ext_Mem_Limit endp ;[]==============================================================[] ;Later_Cache_Sizing: (POST 3Eh) ; Do external cache sizing before diplay cache size to screen ;Save : all but flags ;Input : none ;Output: none ;Note : 1. We do cache sizing just after onboard memory configuration ; detection mostly. If it cann't detect cache sizing ; correctly , you can do it here. ; 2. Stack is available now. ;[]==============================================================[] public Later_Cache_Sizing Later_Cache_Sizing proc near call far ptr X_Later_Cache_Sizing ;R13 ret ; Dummy Return Later_Cache_Sizing endp ;[]==============================================================[] ;Ct_Math_Detect: (POST 0Bh) ; Detect coprocessor presence by special method. ;Save : all but flags and AL ;Input : none ;Output: carry set : No special method ; carry clear: Special detection ; AL - 0 - no coprocessor ; - 1 - 287 ; - 2 - 387 ;Note : 1. Some chipset can not detect coproessor by standard ; method and it offer special register to indicate ; coprocessor presence. In this case, programmer ; should return actual coprocessor value in AL. ; 2. Stack is available now. ;[]==============================================================[] public Ct_Math_Detect Ct_Math_Detect proc near stc ;No special detect ret Ct_Math_Detect endp ;[]==============================================================[] ;Ct_Option_Rom_Scan: (POST 52h) ; Initialize special adaptor ROMs ;Save : all but flags ;Input : none ;Output: none ;Note : 1. Initialize special adaptor ROMs for customerization. ; 2. typically used is to scan E8000-EFFFF ROMs ;[]==============================================================[] public Ct_Option_Rom_Scan Ct_Option_Rom_Scan proc near ret ;no special option ROM Ct_Option_Rom_Scan endp ;[]==============================================================[] ;Ct_Show_Config:(POST 61h) ; Special string display after showing system configuration ;Save : all but flag ;Input : none ;Output: none ;Note : 1. Some customer want to show their own messages after ; system configuration display. ; 2. Please use "Display_String" to display these strings ;[]==============================================================[] public Ct_Show_Config Ct_Show_Config proc near call far ptr X_Ct_Show_Config ret Ct_Show_Config endp ifdef CLEAR_PASSWORD_SUPPORT ;[]==============================================================[] ;Ck_Password_Switch: (POST 0Eh) ; Some board maker design a password switch to clear password ; setting. You can check the switch here, and disable password ; checking and display any messages if switch on. ;Save : all but flag ;Input : none ;Output: none ;Note : 1. This routine is customerization issue. ;[]==============================================================[] public Ck_Password_Switch Ck_Password_Switch proc near call far ptr E000_Ck_Password_Switch ret Ck_Password_Switch endp endif; CLEAR_PASSWORD_SUPPORT ;[]==============================================================[] ;[]==============================================================[] CYRIXREG STRUC db ? ;register index db ? ;register value CYRIXREG ENDS public Cyrix_Cache_Reg public NO_OF_CYRIX_REG Cyrix_Cache_Reg: CYRIXREG <0c0h,002h> ; Dummy Register NO_OF_CYRIX_REG EQU ($ - Cyrix_Cache_Reg) / 2 ;[]========================================================================[] ;Procedure: Ct_Restore_Cyrix_Reg ; ;Function : To restore the Cyrix registers during shutdown or warm-reset. ; ;Input : None ; ;Output : None ; ;Registers: All registers should be preserved ; ;Note : 1. stack available ; 2. Should check if it is M7/M6 before restoring. ; 3. Usually, code to resotre SMBASE reg.(CEh, CFh) is ; placed in this routine. ;[]========================================================================[] Public Ct_Restore_Cyrix_Reg Ct_Restore_Cyrix_Reg Proc Near ret ; Dummy Return Ct_Restore_Cyrix_Reg Endp ifdef Double_Password ;[]========================================================================[] ;Procedure: Ct_User_Password_Location ; ;Function : Claim the CMOS locations for two-layer password operation ; ;Input : None ; ;Output : DI - First CMOS location to store hashed password, this need ; 2 bytes of CMOS ; SI - CMOS location to save password setting flag ; DL - Mask byte for checking password settging ; ; ;Registers: all except DI,SI and DL ; ;Note : 1. stack available ; 2. The programmer should implement this routine to support ; two-layer password. ; 3. The routine must offer 3 bytes of CMOS to caller. ;[]========================================================================[] Public Ct_User_Password_Location Ct_User_Password_Location Proc Near call far ptr E000_Ct_User_Password_Location ret Ct_User_Password_Location Endp ;R06 - start db 'KcMoS' db 62h,64h ;62h-63h dw 0 ;end sign ;R06 - end endif; Double_Password ifdef NEW_IDE_MODE_3 ;[]==============================================================[] ; ; Ct_Set_IDE_Timing: (POST 42h) ; ; Programing I/O chip registre for IDE PIO mode 3 support ; ; SAVES : all ; ; ENTRY : IDE_PARM_Flag[bp] : ; Bit 0 - 3 = drive 0-3 support PIO mode 3 if bit set to 1 ; ; EXIT : None ; ; NOTE : 1. Stack available ; ;[]==============================================================[] public Ct_Set_IDE_Timing Ct_Set_IDE_Timing proc near call far ptr E000_Ct_Set_IDE_Timing ret Ct_Set_IDE_Timing endp endif; NEW_IDE_MODE_3 ;[]==============================================================[] ; Ct_Cache:(POST 61h) ; Turn secondary cache on/off routine. ; Input : AL = Turn on (TRUE) or off (FALSE) cache ; Output : None ; Destroy: C flag ;[]==============================================================[] public Ct_Cache Ct_Cache proc near ret ; Dummy Return Ct_Cache endp ;[]=============================================================[] ;Procedure : Ct_OnChip_IDE_Chk (POST 0Bh)(call from Pci_IO_Mem_Init) ;Function : Return status of On-chip IDE for PCI add-in PCI/IDE ; controlling ; ;Input : none ; ;Output : carry set - OnChip IDE disabled ; no carry - Onchip IDE enabled ;Note : This function should return right status of on-chip ; IDE, otherwise IDE port will be conflicted if ; PCI/IDE card is plugged ;[]=============================================================[] public Ct_OnChip_IDE_Chk Ct_OnChip_IDE_Chk proc near call far ptr X_Ct_OnChip_IDE_Chk ret Ct_OnChip_IDE_Chk endp ;[]=============================================================[] ; Ct_MemHole_Status: ;Function : return memory hole at 15Mb-16Mb status ; ;Input : none ;Output : AL - 0 = hole disabled ; 1 = hole enabled ;[]=============================================================[] public Ct_MemHole_Status Ct_MemHole_Status proc near call far ptr X_Ct_MemHole_Status ret Ct_MemHole_Status endp ifdef PNP_BIOS ;R43 include pnp.equ ;R35 ;[]========================================================================[] ;Procedure: Ct_Pci_Escd ;Function : Return Chipset PCI ESCD ;Input : ES:DI = buffer address pointer ; CH = device/function number ;Output : CF = 0 special PCI ESCD ; CF = 1 not special PCI ESCD ;Note : 1. Don't destroy any register ; 2. Please refer to "2A4X5000.ASM" ;[]========================================================================[] public Ct_Pci_Escd Ct_Pci_Escd proc near call far ptr X_Ct_Pci_Escd ret Ct_Pci_Escd endp endif ;PNP_BIOS ;R22 ;[]==============================================================[] ;R22 ; Get_Set_Ct_OR(Get_Set_PCI_OR): ;R22 ; OR a value in the chipset register. ;R22 ; Input : CX = Index register to change ;R22 ; bl = Value to change (OR) ;R22 ; Output : None ;R22 ; Destory: EAX, ECX, DX ;R22 ; ;R22 ;[]==============================================================[] ;R22 Public Get_Set_Ct_OR, Get_Set_PMU_OR ;R22 Get_Set_Ct_OR proc near ;R22 Get_Set_PMU_OR: ;R22 call Get_Ct ;R22 or al, bl ;OR data ;R22 call Set_Ct ;R22 ret ;R22 Get_Set_Ct_OR endp ;R22 ;R22 ;R21;[]==============================================================[] ;R22 ;R21; Get_Set_Ct_AND(Get_Set_PCI_AND): ;R22 ;R21; AND a value in the chipset register. ;R22 ;R21; Input : CX = Index register to change. ;R22 ;R21; bl = Value to change (AND) ;R22 ;R21; Output : None ;R22 ;R21; Destory: EAX, ECX, DX ;R22 ;R21; ;R22 ;R21;[]==============================================================[] ;R22 ;R21 Public Get_Set_Ct_AND, Get_Set_PMU_AND ;R22 ;R21Get_Set_Ct_AND proc near ;R22 ;R21Get_Set_PMU_AND: ;R22 ;R21 call Get_Ct ;R22 ;R21 and al, bl ;AND data ;R22 ;R21 call Set_Ct ;R22 ;R21 ret ;R22 ;R21Get_Set_Ct_AND endp ;[]==============================================================[] ; Set_Ct_Clear(Set_PCI_Clear): ; Clear a value in the chipset register. ; Input : CX = Index register to change. ; Output : None ; Destory: EAX, ECX, DX ; ;[]==============================================================[] Public Set_Ct_Clear Set_Ct_Clear proc near xor al, al ; Zero call Set_Ct ; Clear ret Set_Ct_Clear endp public Get_CMOS2 Get_CMOS2 proc near OUT 72h,AL ; address to interface jcxz short $+2 IN AL,73h jcxz short $+2 ret Get_CMOS2 endp public Set_CMOS2 Set_CMOS2 proc near OUT 72h,AL ; address to interface jcxz short $+2 xchg al,ah ;ah=index,al=value OUT 73h,AL ; and output it jcxz short $+2 ret Set_CMOS2 endp FCODE ENDS XGROUP GROUP XCODE XCODE SEGMENT USE16 PARA PUBLIC 'XCODE' ASSUME CS:XGROUP,ES:XGROUP ;R50 - starts ;[]==============================================================[] ; X_If_693A: ; Test if 693A Chip ? ; Input : None ; Output : JB : Not 693A ; JNB : Is 693A ; Destory: Flag ;[]==============================================================[] Public X_If_693A X_If_693A Proc Near pushad mov cx,VT692 + 08h call X_Get_Ct cmp al, 40h popad ret X_If_693A Endp ;R50 - ends ;R07 - starts ifdef SMBus_Port ;R46A - starts ;Function : Read a I2C byte value ;Input : BL - I2C ID address,AL - byte index ;Output : AL - value return if carry cleared ; Fail - if carr set Public X_I2C_Byte_Read X_I2C_Byte_Read proc near ;set index byte to read mov dx,SMBus_Port +03h out dx,al ;Index NEWIODELAY ;set I2C ID No. mov dl,04h mov al,bl ;E2PROM read cmd or al,01H ;bit 0=1 for I2C read out dx,al NEWIODELAY ;wait SMbus ready CALL X_Chk_SMBus_READY ;start I2C read operation mov dl,02h mov al,48h out dx,al ;read data NEWIODELAY ;wait for a while mov cx,100h @@: newiodelay loop short @B ;check status OK ? CALL X_Chk_SMBus_READY jc short X_I2CFaile ;SMBus Fail ;read data mov dl,05 ;data port in al,dx ;Data0 NEWIODELAY ;value return in AL X_I2CFaile: ret X_I2C_Byte_Read endp Public X_Chk_SMBus_READY X_Chk_SMBus_READY Proc near mov dx,SMBus_Port + 0 clc mov cx,0100h X_Chk_I2c_OK: in al,dx ;get status NEWIODELAY or al,al jz short X_Clear_final test al,04h jnz short X_SMBus_Err test al,01h ;busy ? jz short X_Not_Smbusy ror ecx,16 mov cx,1000h @@: loop short @B ror ecx,16 X_Not_Smbusy: out dx,al loop short X_Chk_I2c_OK X_SMBus_Err: out dx,al ;clear status NEWIODELAY in al,dx test al,04H ;device error ? jnz short X_SMBus_Err stc X_Clear_final: ret X_Chk_SMBus_READY Endp ;R46A - ends ;R07A ifdef CAS_Latency_Error_String IFNDEF No_Suggested_SDRAM_CL ;R07A X_CAS_Latency_Error_String Proc Far pushad IFDEF CAS_Latency_Auto ;R15 mov si,offset SDRAM_CL_Item ;R15 call X_GetItem_Value ;R15 cmp al,2 ;R15 jz short Dont_Report_ ;R15 Don't report ENDIF;CAS_Latency_Auto ;R15 xor di,di ;R07A xor bh,bh mov bl, 0a0h Test_SPD_Loop_: shr bh,2 mov al, 18 call X_I2C_Byte_Read jnc short Support_SPD_ or bh,80h ;No Support SPD Support_SPD_: test al,02h jnz short Support_2T_ or bh,80h ;No Support 2T Support_2T_: add bl,2 cmp bl,0a6h jbe short Test_SPD_Loop_ ifdef Debug_SPD_Warning mov al,bh out 9eh,al endif; Debug_SPD_Warning mov cx, VT692+60h call X_Get_Ct and al,bh jz short All_SDRAM_Support_2T_ mov si,offset SDRAM_CL_Item call X_GetItem_Value or al,al jz short Dont_Report_ ; Don't report ;R07A or byte ptr OEM_Error_CMOS2[bp], OEM_Error_CMOS_Bits2 or di,01h ;R07A jmp short No_SDRAM_Pluged_ All_SDRAM_Support_2T_: ;R07A - starts mov si,offset SDRAM_CL_Item call X_GetItem_Value or al,al jnz short No_SDRAM_Pluged_ ; Don't report call X_Check_SDRAM jnz short No_SDRAM_Pluged_ or di,02h No_SDRAM_Pluged_: ;---------------; ; Report ; ;---------------; or di,di jz short Dont_Report_ call Far Ptr E000_Show_CAS_Latency_Error_String Dont_Report_: ;R07A - ends popad ret X_CAS_Latency_Error_String endp ;R46A ;Function : Read a I2C byte value ;R46A ;Input : BL - I2C ID address,AL - byte index ;R46A ;Output : AL - value return if carry cleared ;R46A ; Fail - if carr set ;R46A ;R46A Public X_I2C_Byte_Read ;R46A X_I2C_Byte_Read proc near ;R46A ;R46A ;set index byte to read ;R46A mov dx,SMBus_Port +03h ;R46A out dx,al ;Index ;R46A NEWIODELAY ;R46A ;R46A ;set I2C ID No. ;R46A mov dl,04h ;R46A mov al,bl ;E2PROM read cmd ;R46A or al,01H ;bit 0=1 for I2C read ;R46A out dx,al ;R46A NEWIODELAY ;R46A ;R46A ;wait SMbus ready ;R46A CALL X_Chk_SMBus_READY ;R46A ;R46A ;start I2C read operation ;R46A mov dl,02h ;R46A mov al,48h ;R46A out dx,al ;read data ;R46A NEWIODELAY ;R46A ;R46A ;wait for a while ;R46A mov cx,100h ;R46A @@: ;R46A newiodelay ;R46A loop short @B ;R46A ;R46A ;check status OK ? ;R46A CALL X_Chk_SMBus_READY ;R46A jc short X_I2CFaile ;SMBus Fail ;R46A ;R46A ;read data ;R46A mov dl,05 ;data port ;R46A in al,dx ;Data0 ;R46A NEWIODELAY ;R46A ;value return in AL ;R46A ;R46A X_I2CFaile: ;R46A ret ;R46A X_I2C_Byte_Read endp ;R46A ;R46A Public X_Chk_SMBus_READY ;R46A X_Chk_SMBus_READY Proc near ;R46A ;R46A mov dx,SMBus_Port + 0 ;R46A clc ;R46A mov cx,0100h ;R46A X_Chk_I2c_OK: ;R46A in al,dx ;get status ;R46A NEWIODELAY ;R46A or al,al ;R46A jz short X_Clear_final ;R46A ;R46A test al,04h ;R46A jnz short X_SMBus_Err ;R46A ;R46A test al,01h ;busy ? ;R46A jz short X_Not_Smbusy ;R46A ror ecx,16 ;R46A mov cx,1000h ;R46A @@: ;R46A loop short @B ;R46A ror ecx,16 ;R46A X_Not_Smbusy: ;R46A out dx,al ;R46A loop short X_Chk_I2c_OK ;R46A X_SMBus_Err: ;R46A out dx,al ;clear status ;R46A NEWIODELAY ;R46A in al,dx ;R46A test al,04H ;device error ? ;R46A jnz short X_SMBus_Err ;R46A ;R46A stc ;R46A X_Clear_final: ;R46A ;R46A ret ;R46A X_Chk_SMBus_READY Endp ;R07A endif; CAS_Latency_Error_String ENDIF; No_Suggested_SDRAM_CL ;R07A ;R46 - starts IFNDEF No_Suggested_DRAM_Clock X_DRAM_Clock_Error_String Proc Far pushad ;R50 mov cx,VT692 + 08h ;R50 call X_Get_Ct ;R50 cmp al, 40h call X_If_693A ;R50 jb Dont_Report_1 ; Not 133Mhz Support ! call X_Check_SDRAM jnz Dont_Report_1 ; No SDRAM Pluged ! xor bh,bh mov bl, 0a0h Test_SPD_Loop_1: shr bh,2 mov al, 9 ; Read Byte 9 : call X_I2C_Byte_Read or al,al jz Support_66MHz_DRAM ; 00h => Support 66MHz cmp al,75h jbe Support_133MHz_DRAM ; 01h - 75h => Support 133MHz cmp al,0A0h jbe Support_100MHz_DRAM ; 75h - A0h => Support 100MHz Support_66MHz_DRAM: or bh,0C0h ;Support 66MHz Support_100MHz_DRAM: or bh, 80h ;Support 100MHz Support_133MHz_DRAM: ;Support 133MHz add bl,2 cmp bl,0a6h jbe short Test_SPD_Loop_1 ifdef Debug_DRAM_CLK_Warning mov al,bh out 9eh,al endif; Debug_DRAM_CLK_Warning mov cx, VT692+60h call X_Get_Ct and al,bh jz short All_SDRAM_Support_133MHz and al,55h jz short SDRAM_Support_100MHz ;-----------------------; ; Support 66MHz ; ;-----------------------; call X_Measure_SDRAM_Speed cmp al,66 jz short Dont_Report_1 ; Don't report mov bl,01h jmp short Report_Warning SDRAM_Support_100MHz: ;-----------------------; ; Support 100MHz ; ;-----------------------; call X_Measure_SDRAM_Speed cmp al,100 jz short Dont_Report_1 ; Don't report mov bl,02h jmp short Report_Warning All_SDRAM_Support_133MHz: ;R07A - starts ;-----------------------; ; Support 133MHz ; ;-----------------------; call X_Measure_SDRAM_Speed cmp al,133 jz short Dont_Report_1 ; Don't report mov bl,04h Report_Warning: ;---------------; ; Report ; ;---------------; call Far Ptr E000_Show_DRAM_Clock_Error_String Dont_Report_1: ;R07A - ends popad ret X_DRAM_Clock_Error_String Endp ENDIF; No_Suggested_DRAM_Clock ;R46 - ends endif; SMBus_Port ;R07 - ends ;R46 - starts ;R50 ifndef No_Suggested_DRAM_Clock Public X_Measure_SDRAM_Speed ;R50 X_Measure_SDRAM_Speed Proc Near mov cx, VT692 + 68h call X_Get_Ct and al,03h mov bl,al mov cx, VT692 + 69h call X_Get_Ct and al,0C0h shr al,4 or bl,al mov al,66 mov si,offset SDRAM_Speed_TBL Search_Loop: cmp byte ptr cs:[si],bl jz short Have_Searched cmp byte ptr cs:[si],0FFh jz short Search_Over add si,2 jmp short Search_Loop Have_Searched: mov al,byte ptr cs:[si+1] ; Get speed from table. Search_Over: ifdef Debug_Measure_SDRAM_Speed out 9eh,al endif; Debug_Measure_SDRAM_Speed ret X_Measure_SDRAM_Speed Endp SDRAM_Speed_TBL: db 00000b, 66 db 01001b, 66 db 00100b, 100 db 00001b, 100 db 01010b, 100 db 01011b, 100 db 00101b, 133 db 00010b, 133 db 00011b, 133 db 0FFh ; End of Table ! ;R50 endif; No_Suggested_DRAM_Clock ;R46 - ends ifdef PNP_BIOS X_Ct_Pci_Escd Proc Far push cx push si push di push ds mov si, cs mov ds, si cmp ch, 38h jne short Ct_Pci_Escd_Fail xor si, si mov cx,VT586_IDE + 40H F000_call Get_Ct test al,02h ;if IDE Primary Enable ? jz short @f ;No, skip or si, 1 ;Yes, Table_Index + 1 @@: mov cx,VT586_IDE + 40H F000_call Get_Ct test al,01h ;if IDE Secondary Enable ? jz short @f ;No, skip or si, 2 ;Yes, Table_Index + 2 @@: add si, si ;word add si, offset ESCD_PCIB2_TBL mov si, cs:[si] mov cx, cs:[si] rep movsb clc jmp short Ct_Pci_Escd_Exit Ct_Pci_Escd_Fail: stc Ct_Pci_Escd_Exit: pop ds pop di pop si pop cx ret X_Ct_Pci_Escd endp ;---------------; ; IDE Disable ; ;---------------; BRDDEF 0, 0, 4040h, ESCD_PCIB2_1 FUNCDEF FUNC_DISABLE FUNCDEF FUNC_DISABLE FUNCDEF ECD_FF ECDHEAD PCI_BRD ECDPCI 0, ((VT586)SHR(8)), 0586h, 1106h ECDPCI 0, ((VT586_IDE)SHR(8)), 0571h, 1106h ECDEND BRDEND ;---------------; ; Primary IDE ; ;---------------; BRDDEF 0, 0, 4040h, ESCD_PCIB2_2 FUNCDEF FUNC_DISABLE FUNCDEF IRQ_ENTRY+IO_ENTRY IRQESCD 00000000b, 14 ;IRQ14 IOESCD 10000000b, 1F0h, 10h ;1F0-1FF IOESCD 00000000b, 3F6h, 1 ;3F6 FUNCDEF ECD_FF ECDHEAD PCI_BRD ECDPCI 0, ((VT586)SHR(8)), 0586h, 1106h ECDPCI 0, ((VT586_IDE)SHR(8)), 0571h, 1106h ECDEND BRDEND ;---------------; ; Secondary IDE ; ;---------------; BRDDEF 0, 0, 4040h, ESCD_PCIB2_3 FUNCDEF FUNC_DISABLE FUNCDEF IRQ_ENTRY+IO_ENTRY IRQESCD 00000000b, 15 ;IRQ15 IOESCD 10000000b, 170h, 10h ;170-17F IOESCD 00000000b, 376h, 1 ;376 FUNCDEF ECD_FF ECDHEAD PCI_BRD ECDPCI 0, ((VT586)SHR(8)), 0586h, 1106h ECDPCI 0, ((VT586_IDE)SHR(8)), 0571h, 1106h ECDEND BRDEND ;---------------; ; Both Channel ; ;---------------; BRDDEF 0, 0, 4040h, ESCD_PCIB2_4 FUNCDEF FUNC_DISABLE FUNCDEF IRQ_ENTRY+IO_ENTRY IRQESCD 10000000b, 14 ;IRQ14 IRQESCD 00000000b, 15 ;IRQ15 IOESCD 10000000b, 1F0h, 10h ;1F0-1FF IOESCD 10000000b, 3F6h, 1 ;3F6 IOESCD 10000000b, 170h, 10h ;170-17F IOESCD 00000000b, 376h, 1 ;376 FUNCDEF ECD_FF ECDHEAD PCI_BRD ECDPCI 0, ((VT586)SHR(8)), 0586h, 1106h ECDPCI 0, ((VT586_IDE)SHR(8)), 0571h, 1106h ECDEND BRDEND ESCD_PCIB2_TBL label word dw offset ESCD_PCIB2_1 dw offset ESCD_PCIB2_2 dw offset ESCD_PCIB2_3 dw offset ESCD_PCIB2_4 endif ;PNP_BIOS ;[]==============================================================[] ; _get_ct(Get_PCI): ; Reads a value directly from the chipset register. ; ; Input : CX = Index register to read ; Output : AL = Value read ; Destory: EAX, DX ;[]==============================================================[] Public X_get_ct X_get_ct proc near F000_call Get_Ct ret X_get_ct endp ;[]==============================================================[] ; X_set_ct(Set_PCI): ; Changes a value in the chipset register. ; Input : CX = Index register to change ; AL = Value to change ; Output : None ; Destory: EAX, ECX, DX ; ;[]==============================================================[] Public X_set_ct X_set_ct proc near push cx ;R29 F000_call Set_Ct pop cx ;R29 ret X_set_ct endp ;[]==============================================================[] ; X_get_set_ct(Get_Set_PCI): ; Changes a value in the chipset register. ; Input : CX = Index register to change ; bx = Value to change ; Output : None ; Destory: EAX, ECX, DX ; ;[]==============================================================[] Public X_Get_Set_Ct X_Get_set_ct proc near ;R29 F000_call Get_Set_Ct call X_Get_Ct ;R29 and al, bl ;R29 AND data or al, bh ;R29 OR data call X_Set_Ct ;R29 ret X_Get_set_ct endp ;[]==============================================================[] ; X_Get_Set_Ct_OR(Get_Set_PCI_OR): ; Changes a value in the chipset register. ; Input : CX = Index register to change ; bl = Value to change (OR) ; Output : None ; Destory: EAX, ECX, DX ; ;[]==============================================================[] Public X_Get_Set_Ct_OR X_Get_Set_Ct_OR proc near call X_Get_Ct or al, bl ;OR data call X_Set_Ct ret X_Get_Set_Ct_OR endp ;[]==============================================================[] ; X_Get_Set_Ct_AND(Get_Set_PCI_AND): ; Changes a value in the chipset register. ; Input : CX = Index register to change. ; bl = Value to change (AND) ; Output : None ; Destory: EAX, ECX, DX ; ;[]==============================================================[] Public X_Get_Set_Ct_AND X_Get_Set_Ct_AND proc near call X_Get_Ct and al, bl ;AND data call X_Set_Ct ret X_Get_Set_Ct_AND endp ;[]==============================================================[] ; X_Set_Ct_Clear(_Set_PCI_Clear): ; Clear a value in the chipset register. ; Input : CX = Index register to change. ; Output : None ; Destory: EAX, ECX, DX ; ;[]==============================================================[] Public X_Set_Ct_Clear X_Set_Ct_Clear proc near xor al,al ; Zero call X_Set_Ct ; Clear ret X_Set_Ct_Clear endp ;[]==============================================================[] ; X_get_PMIO: ; Reads a value directly from the chipset register. ; ; Input : CX = Index value of IO port ; Output : AL = Value read ; Destory: EAX ;[]==============================================================[] Public X_Get_PMIO X_Get_PMIO proc near F000_call Get_PMIO ret X_Get_PMIO endp ;[]==============================================================[] ; X_set_pmio: ; Changes a value in the chipset register. ; Input : CX = Index port to change ; AL = Value to change ; Output : None ; Destory: EAX ; ;[]==============================================================[] Public X_Set_PMIO X_Set_PMIO proc near F000_call Set_PMIO ret X_Set_PMIO endp ;[]==============================================================[] ; X_Get_set_pmio: ; Changes a value in the chipset register. ; Input : CX = Index port to change ; AX = Value to change, AL: AND Value, AH : OR value ; Output : None ; Destory: EAX ; ;[]==============================================================[] Public X_Set_PMIO X_Get_Set_PMIO proc near Post_Func_call E000_Get_Set_PMIO ret X_Get_Set_PMIO endp ;[]==============================================================[] ; X_Get_set_pmio_OR: ; Changes a value in the chipset register. ; Input : CX = Index port to change ; AL : OR value ; Output : None ; Destory: EAX ; ;[]==============================================================[] Public X_Get_Set_PMIO X_Get_Set_PMIO_OR proc near Post_Func_call E000_Get_Set_PMIO_OR ret X_Get_Set_PMIO_OR endp ;[]==============================================================[] ; X_Get_set_pmio_AND: ; Changes a value in the chipset register. ; Input : CX = Index port to change ; AX = Value to change, AL: AND Value, AH : OR value ; Output : None ; Destory: EAX ; ;[]==============================================================[] Public X_Get_Set_PMIO_AND X_Get_Set_PMIO_AND proc near Post_Func_call E000_Get_Set_PMIO_AND ret X_Get_Set_PMIO_AND endp ifdef SMBus_Port Public X_Ct_Get_Row_Map X_Ct_Get_Row_Map Proc Near mov cx,VT692+60h ; AL : bit0/1 bit2/3 bit4/5 call X_Get_CT ; Bank : 0/1 2/3 4/5 ; if '10b' mean SDRAM ! test al, 02h jnz short @f and al, not 01h @@: test al, 08h jnz short @f and al, not 04h @@: test al, 20h jnz short @f and al, not 10h @@: ret X_Ct_Get_Row_Map Endp endif; SMBus_Port ifdef Boot_Password ;[]===========================================================[] ;[]===========================================================[] public Ct_SAVE_BOOT_PASSWORD Ct_SAVE_BOOT_PASSWORD Proc Near pusha mov bx, ax mov al,BOOTPASS_LOC1 mov ah,bl F000_Call Set_CMOS2 mov al,BOOTPASS_LOC2 mov ah,bh F000_Call Set_CMOS2 popa ret Ct_SAVE_BOOT_PASSWORD Endp Cmp_BootPassword proc near mov bx, ax ror ebx,16 mov al,BOOTPASS_LOC1 F000_Call Get_CMOS2 mov bl,al mov al,BOOTPASS_LOC2 F000_Call Get_CMOS2 mov bh,al ror ebx,16 mov ax,bx ror ebx,16 cmp ah,bh jne short @F cmp al,bl @@: ret Cmp_BootPassword endp public xVerify_BootPass xVerify_BootPass proc far push word ptr ATTRIBUTE[bp] push word ptr TEMP_YEAR[bp] push ds mov si, SEG DGROUP mov ds, si test byte ptr BOOTPASS_CMOS[bp], BOOTPASS_CMOS_BIT ;booting need pass? jz Verify_Pass_Exit ;no, exit mov ax,3 int 10h extrn Backup_pass_screen:near call Backup_pass_screen Chk_Super_Pass: mov byte ptr CUR_PAGE[bp], 0 ; don't update time mov word ptr LAST_KEY[bp], 0 ; dummy word extrn Get_Password:near call Get_Password call Cmp_BootPassword je Password_Valid extrn Error_PassWord:near Call Error_PassWord jmp Chk_Super_Pass Password_Valid: extrn Restore_pass_screen:near call Restore_pass_screen Verify_Pass_Exit: pop ds pop word ptr TEMP_YEAR[bp] ;use this word pop word ptr ATTRIBUTE[bp] retf xVerify_BootPass endp endif; Boot_Password X_CT_FINAL_INIT Proc Far ifdef Have_BankInterleave_Item ifdef Have_Page_Mode_Item pusha ;---------------------------------------; ; Set DRAM Page Mode ; ;---------------------------------------; mov si,offset DRAM_Page_Mode_Item call X_GetItem_Value or al,al jz short Disable_DRAM_Page_Mode call Test_DRAM ;If Fast Page DRAM exist ? cmp al,1 ; jz short Disable_DRAM_Page_Mode ;Yes, jmp ! ifdef Disable_Page_When_100MHz call X_If_100MHz_DRAM_Clock ; if 100MHz ? jc short Disable_DRAM_Page_Mode ; Yes, jmp ! endif; Disable_Page_When_100MHz mov cx, VT692+6bh mov bl, 01h ;RX6b[0]=1 call X_Get_Set_Ct_OR ifndef No_Only_EDO_Page_Mode call X_check_sdram ; If SDRAM DRAM exist ? jnz short Only_EDO_Page_Mode ; No, jmp ! endif; No_Only_EDO_Page_Mode mov si,offset SDRAM_BK_Item call X_GetItem_Value or al,al ; If set Disable? jz short Disable_DRAM_Page_Mode ; Yes, jmp! mov bh, al mov bl, al or bl, 0FCh ; mask bit 1,0 mov cx, VT692+60h ; call X_Get_Ct ; mov si,ax ;Save DRAM type to SI. test si,02h ; Enable Bank Interleave jz short @f ; according to your setting. mov cx, VT692+64h ; call X_Get_Set_Ct ; @@: ; test si,08h ; jz short @f ; mov cx, VT692+65h ; call X_Get_Set_Ct ; @@: ; test si,20h ; jz short @f ; mov cx, VT692+66h ; call X_Get_Set_Ct ; @@: Only_EDO_Page_Mode: mov cx, VT692+68h ; mov bl, 0c0h ; RX68[6,7]=11b call X_Get_Set_Ct_OR ; Disable_DRAM_Page_Mode: popa endif; Have_Page_Mode_Item endif; Have_BankInterleave_Item ifdef Disable_Page_Mode_When_Over_75MHz Call X_If_100MHz_DRAM_Clock ; if 100MHz ? jc short Disable_DRAM_Page_Mode_ ; Yes, jmp ! jmp short @f Disable_DRAM_Page_Mode_: mov cx, VT692+6bh mov bl, not 01h ;RX6b[0]=0 call X_Get_Set_Ct_AND @@: endif; Disable_Page_Mode_When_Over_75MHz ;-------------------------------; ; PCI Master Read Prefetch ; ; by enhanced command ; ; VT692_PP RX42[7] = ; ; VT692 RX74[7] ; ;-------------------------------; mov cx, VT692+74h call X_Get_Ct and al,80h mov bh,al mov cx, VT692_PP+42h mov bl,7fh call X_Get_Set_Ct ;-------------------------------; ; Set Delay Transaction ; ;-------------------------------; xor bx, bx mov si, offset Delay_Trans_Item call X_GetItem_Value or al, al jz short @F mov bh, 46h ; 47[6][2][1] @@: mov cx, VT586+47h call X_Get_Ct and al, NOT 046h or al, bh call X_Set_Ct ifdef Patch_Old_IDE_Driver_When_IDE_Disabled ;-------------------------------; ; Set Register if IDE Disable ; ;-------------------------------; ;Disable command register if both IDE channel are disabled mov cx,VT586_IDE+40H ;check if both IDE disabled call X_Get_Ct test al,11b ;both channel disabled ? jnz short AtLeast_OneCh mov cx,VT586_IDE+4H ;command register call X_Set_Ct_Clear ;disable I/O & Mem. access AtLeast_OneCh: mov cx,VT586_IDE+3cH ;set no IRQ required call X_Set_Ct_Clear mov cx,VT586_IDE+45H mov bl, 10h ;lock register 3CH call X_Get_Set_Ct_OR mov ax,VT586_IDE+20H ;Read Bus Master Bus Address mov dx,0cf8h ; out dx,eax ; add dx,4 ; in ax,dx ; and ax, not 03h ; mov dx,ax ; add dx,02h ; Addr + 2 = Channel 0 mov al,60h ; bit 6,5 = 1 out dx,al add dx,08h ; Addr + 10 = Channel 1 out dx,al endif; Patch_Old_IDE_Driver_When_IDE_Disabled ifdef VT586_USB ifdef USB2_Separate_Control ;R31 - starts ;-----------------------; ; En/Disable USB 1 ; ;-----------------------; mov bx, 00FBh ; Set Enable USB mov si,offset ONBD_USB_Item call X_Getitem_Value ;R31A ;R31A call F000_Getitem_Value or al,al jz short @f ; if Enable, jmp! mov bx, 04FFh ; Set Disable USB mov cx, VT586_USB+3Ch call X_Set_Ct_Clear ;R31A disable USB IO ;R31A call _Set_Ct_Clear ;disable USB IRQ mov cx, VT586_USB+04h call X_Set_Ct_Clear ;R31A disable USB IO ;R31A call _Set_Ct_Clear ;disable USB IO @@: mov cx, VT586 + 48h ; Set Onchip USB En/Disable call X_Get_Set_Ct ;R31A ;R31A call _Get_Set_Ct ;-----------------------; ; En/Disable USB 2 ; ;-----------------------; mov bx, 00EFh ; Set Enable USB 2 mov si,offset ONBD_USB_2_Item call X_Getitem_Value ;R31A ;R31A call F000_Getitem_Value or al,al jz short @f ; if Enable, jmp! mov bx, 10FFh ; Set Disable USB 2 mov cx, VT586_USB_2+3Ch call X_Set_Ct_Clear ;R31A ;R31A call _Set_Ct_Clear ;disable USB 2 IRQ mov cx, VT586_USB_2+04h call X_Set_Ct_Clear ;R31A ;R31A call _Set_Ct_Clear ;disable USB 2 IO @@: mov cx, VT586 + 85h ; Set Onchip USB 2 En/Disable call X_Get_Set_Ct ;R31A ;R31A call _Get_Set_Ct ; else; USB2_Separate_Control ;R31 - ends ;-------------------------------; ; Disable USB IO if USB Disable ; ;-------------------------------; mov bx, 00FBh ; Set Enable USB ifdef VT586_USB_2 ;R28 mov di, 00EFh ;R28 Set Enable USB 2 endif; VT586_USB_2 ;R28 mov si,offset ONBD_USB_Item call X_Getitem_Value or al,al jz short @f ; if Enable, jmp! mov bx, 04FFh ; Set Disable USB ifdef VT586_USB_2 ;R28 mov di, 10FFh ;R28 Set Disable USB 2 endif; VT586_USB_2 ;R28 mov cx, VT586_USB+3Ch call X_Set_Ct_Clear ;disable USB IRQ mov cx, VT586_USB+04h call X_Set_Ct_Clear ;disable USB IO ifdef VT586_USB_2 ;R28 mov cx, VT586_USB_2+3Ch ;R28 call X_Set_Ct_Clear ;R28 disable USB 2 IRQ mov cx, VT586_USB_2+04h ;R28 call X_Set_Ct_Clear ;R28 disable USB 2 IO endif; VT586_USB_2 ;R28 @@: mov cx, VT586 + 48h ; Set Onchip USB En/Disable call X_Get_Set_Ct ifdef VT586_USB_2 ;R28 mov bx,di ;R28 mov cx, VT586 + 85h ;R28 Set Onchip USB 2 En/Disable call X_Get_Set_Ct ;R28 endif; VT586_USB_2 ;R28 endif; USB2_Separate_Control ;R31 endif ;VT586_USB ;-----------------------; ; En/Disable AGP ; ;-----------------------; ifdef Have_AGP_Item mov si, offset AGP_Item call X_Getitem_Value or al, al jz NO_AGP_VGA endif; Have_AGP_Item mov cx, VT692+80h ;Enable AGP mov bx, 0fffh call X_Get_Set_Ct ifdef Have_AGP_Item NO_AGP_VGA: endif; Have_AGP_Item ;---------------; ; Other ; ;---------------; ifdef Have_DMA_Line_Buffer_Item mov si,offset DMA_Line_Buffer_Item call X_GetItem_Value mov bx,007Fh ; Force Disable or al,al jz short @f ; If Item Set Disable, Jmp ! mov bh,80h ; to Enabled. @@: mov cx,VT586 + 45h ; Set DMA to PCI Line Buffer call X_Get_Set_Ct ; endif; Have_DMA_Line_Buffer_Item ifdef PS2_SETUPABLE ifdef Release_IRQ12_By_MIRQ0 mov si,offset PS2_select_item call X_GetItem_Value or al,al jnz short @f mov cx,VT586 + 55h ; Set MIRQ0 mov bl, 0Ch ; = IRQ12 call X_Get_Set_Ct_OR ; Rlease IRQ12 to ISA Bus @@: endif ;Release_IRQ12_By_MIRQ0 endif ;PS2_SETUPABLE ifdef Disable_PCI_To_CPU_Write_Buffer_When_Cirrus5446 mov dx,1013H ;Cirrus vendor ID mov cx,00B8H ;5434 device ID xor si,si ;first device mov ax,0b102H ;find PCI device func. call int 1AH mov bx, 007Fh ; Disable PCI to CPU Wite Buffer. jnc short Is_Cirrus_5446 endif; Disable_PCI_To_CPU_Write_Buffer_When_Cirrus5446 mov bx, 007Fh ; Disable PCI to CPU Wite Buffer. ifndef NO_Disable_PCI_To_CPU_Write_Buffer_When_100MHz call X_If_100MHz_DRAM_Clock ; if 100MHz ? jc short @f ; Yes, Jmp ! endif; NO_Disable_PCI_To_CPU_Write_Buffer_When_100MHz mov bx, 00FFh ; Enable PCI to CPU Wite Buffer. @@: Is_Cirrus_5446: mov cx,VT692 + 70h ; PCI Buffer Control call X_Get_Set_Ct mov dx,1013H ;Cirrus vendor ID mov cx,00D6H ;5465 AGP device ID xor si,si ;first device mov ax,0b102H ;find PCI device func. call int 1AH jc short No_Cirrus_5465 mov ch, bl ;If Have Cirrus 5465 AGP => mov cl, 0Dh ;Set Latency Timer to 'F0h' mov al, 0F0h F000_call ASet_CfgSpace_Byte No_Cirrus_5465: ifdef Have_ACPI_IO_Node_Item pushad push ds push es extrn E_F000_Shadow_W:near extrn E_F000_Shadow_R:near extrn ACPI_IO_Node_Item:near mov si, offset DGROUP:ACPI_IO_Node_Item call X_GetItem_Value or al, al ; if Setup set Disabled ? jnz short Enable_ACPI_IO_Node ; No, Jmp ! Disable_ACPI_IO_Node: post_func_call E_F000_Shadow_W mov ax,0F000H mov ds,ax mov es,ax extrn VIA_ACPI_IO_Node_Index:near ;PNPBIOS.ASM mov di,offset DGROUP:VIA_ACPI_IO_Node_Index mov ax,0079H ;END_DSP stosw stosw stosw Enable_ACPI_IO_Node: post_func_call E_F000_Shadow_R pop es pop ds popad endif; Have_ACPI_IO_Node_Item mov cx, VT692 + 0dh ; Latency Time of north ;R38 mov al, 10h ; bridge set to 10h ;R38 call X_Set_Ct ; call X_Set_Ct_Clear ;R38 ;R25 - start ;Set F0000-FFFFF region cacheability according to CMOS setup mov si,offset BiosCache_Item call X_GetItem_Value or al,al ;bios cache enabled ? mov ebx,0 ;assume UC(F0000-FFFFF) jz short UnCache_Bios mov ebx,04040404H ;set memory type to WT in lower 32bit UnCache_Bios: mov eax,ebx ;set memory type to WT in lower 32bit mov edx,ebx mov ecx,26EH ;address(26EH) for F0000-F7FFF WRMSR xor al,al ;set UC in F8000-F8FFF ;R25A mov cx,26FH ;address(26FH) for F8000-FFFFF WRMSR ;R25 - end mov cx, VT692+70h ;PCI#2's read caching/delay transaction call X_Get_Ct ; = PCI#1's shr al, 01h and al, 03h mov bl, al mov cx, VT692_PP+40h call X_Get_Set_Ct_OR mov ecx, 202h Find_Empty_MTRR_PhysBase: RDMSR cmp eax, 0h jz short Found_Empty_MTRR_PhysBase cmp cl, 0eh je short NO_WC add cl, 2 jmp short Find_Empty_MTRR_PhysBase Found_Empty_MTRR_PhysBase: mov eax, 80000010h mov dx, 0cf8h out dx, eax mov dl, 0fch in eax, dx and al, NOT 0fh or al, 01h mov edx, 0h WRMSR push ecx mov cx, VT692+84h call X_Get_Ct shl eax, 20 or eax, 0f0000800h mov edx, 0fh pop ecx inc cl WRMSR NO_WC: ifdef Onboard_AGP_SubVendor_ID mov bh,1 ;set bus No. mov cx,(0 SHL 11)+4ch extrn ASet_CfgSpace_Word:near mov ax,Onboard_AGP_SubVendor_ID F000_CALL DGROUP:ASet_CfgSpace_Word endif; Onboard_AGP_SubVendor_ID ifdef Onboard_AGP_SubDevice_ID mov bh,1 ;set bus No. mov cx,(0 SHL 11)+4eh extrn ASet_CfgSpace_Word:near mov ax,Onboard_AGP_SubDevice_ID F000_CALL DGROUP:ASet_CfgSpace_Word endif; Onboard_AGP_SubDevice_ID ;R19 - start ifdef GPO_LOW_BEFORE_BOOT mov bl,GPO_LOW_BEFORE_BOOT ;GPO number post_func_call E000_GPO_Pin_Low ;output GPO low endif; GPO_LOW_BEFORE_BOOT ifdef GPO_HIGH_BEFORE_BOOT extrn E000_GPO_Pin_High:near mov bl,GPO_HIGH_BEFORE_BOOT ;GPO number post_func_call E000_GPO_Pin_High ;output GPO high endif; GPO_HIGH_BEFORE_BOOT ;R19 - end ;R36 start ifdef PCISLOT_MASTER_CONTROL mov si,offset PCI_CONFIG1_Item call X_GetItem_Value or al,al jnz short CHKSlot2 mov cx,(SLOT1_ID shl 11) call BusMasterOff CHKSlot2: mov si,offset PCI_CONFIG2_Item call X_GetItem_Value or al,al jnz short CHKSlot3 mov cx,(SLOT2_ID shl 11) call BusMasterOff CHKSlot3: mov si,offset PCI_CONFIG3_Item call X_GetItem_Value or al,al jnz short CHKover mov cx,(SLOT3_ID shl 11) call BusMasterOff CHKover: endif ;PCISLOT_MASTER_CONTROL ;R36 end ;R47 - starts ;R47B ifdef VT686 ifdef VIA_Y2K_Patch ;R47A ifndef PATCH_WILLIT_YEAR2000 ;-----------------------; ; Enable Y2K Patch ; ;-----------------------; mov al, 32h ; Save SMOS 32h to BH out 70h,al in al,71h mov bh,al mov cx, VT586 + 5Bh ; Reg 5Bh[3] set 1 mov bl, 08h ; call X_Get_Set_Ct_OR ; mov al, 32h ; Restire SMOS 32h to BH out 70h,al mov al,bh out 71h,al endif; PATCH_WILLIT_YEAR2000 endif; VIA_Y2K_Patch ;R47A ;R47B endif; VT686 ;R47 - ends clc ret X_Ct_FINAL_INIT Endp ;R36 start ifdef PCISLOT_MASTER_CONTROL BusMasterOff proc near push cx add cl,0Bh call X_Get_Ct mov si, offset Bridge_TBL pop cx @@: cmp byte ptr CS:[SI],0ffh ;table end? je short MasterOff cmp al,byte ptr CS:[SI] je short MasterOn inc si jmp short @B MasterOff: add cl,4 call X_Get_Ct and al, not 04 call X_Set_Ct MasterOn: ret BusMasterOff ENDP Bridge_TBL: db 01h ;SCSI or Mass storage db 02h ;Lan db 06h ;Bridge db 0FFh endif ;PCISLOT_MASTER_CONTROL ;R36 end ;[]=============================================================[] ;X_Check_SDRAM: check sdram exist or not ;Input: None ;Output: Zero Flag = 0 -- No SDRAM (NZ) ; ELSE -- SDRAM (ZE) ; ;[]=============================================================[] public X_Check_SDRAM X_Check_SDRAM proc near pushad mov bh, 0 mov cx, VT692+60h call X_Get_Ct mov ah, al @@: xor al, al shr ax, 2 mov bl, 0 cmp al, 0C0h jz short sdram_ret inc bh cmp bh, 4 jb short @B mov bl, 4 sdram_ret: or bl, bl popad ret X_Check_SDRAM endp ;[]==============================================================[] ;X_Ct_Show_Config: ; Special string display after showing system configuration ;Save : all but flag ;Input : none ;Output: none ;Note : 1. Some customer want to show their own messages after ; system configuration display. ; 2. Please use "Display_String" to display these strings ;[]==============================================================[] ifdef NEW_DRAM_TYPE_SHOW RAM_TYPE_0 db 'EDO DRAM at Bank :',0 RAM_TYPE_1 db 'SDRAM at Bank :',0 IFDEF DRAM_Bank_Show_As_SIMM ;R05 - starts ;R05A BANK0 db '01 ',0 ;R05A BANK1 db '23 ',0 ;R05A BANK2 db '45 ',0 ;R05A BANK3 db '67 ',0 BANK0 db '0 ',0 ;R05A BANK1 db '1 ',0 ;R05A BANK2 db '2 ',0 ;R05A BANK3 db '3 ',0 ;R05A BANK4 db '4 ',0 ;R05A BANK5 db '5 ',0 ;R05A BANK6 db '6 ',0 ;R05A BANK7 db '7 ',0 ;R05A ELSE; DRAM_Bank_Show_As_SIMM ;R05 - ends BANK0 db '0 ',0 BANK1 db '1 ',0 BANK2 db '2 ',0 BANK3 db '3 ',0 ENDIF; DRAM_Bank_Show_As_SIMM ;R05 ;R34 - starts IFDEF SHOW_ECC_FUNC ECC_TITLE db 'ECC Function :',0 ECC_EN_VAL db 'Enabled',0 ECC_DIS_VAL db 'Disabled',0 ENDIF; SHOW_ECC_FUNC ;R34 - ends else; NEW_DRAM_TYPE_SHOW ifdef SPECIAL_DRAM_TYPE RAM_TYPE_0 db 'SIMM1/2 DRAM Type :',0 RAM_TYPE_1 db 'SIMM3/4 DRAM Type :',0 RAM_TYPE_2 db 'SIMM4/5 DRAM Type :',0 else; SPECIAL_DRAM_TYPE ifdef SPECIAL_DRAM_TYPE_2 RAM_TYPE_0 db 'Bank 0 :',0 RAM_TYPE_1 db 'Bank 1 :',0 RAM_TYPE_2 db 'Bank 2 :',0 else; SPECIAL_DRAM_TYPE_2 ifdef Ocean_SPECIAL_DRAM_TYPE RAM_TYPE_0 db 'Bank0 DRAM Type :',0 RAM_TYPE_1 db 'Bank1 DRAM Type :',0 RAM_TYPE_2 db 'Bank2 DRAM Type :',0 else; Ocean_SPECIAL_DRAM_TYPE RAM_TYPE_0 db 'Bank0/1 DRAM Type :',0 RAM_TYPE_1 db 'Bank2/3 DRAM Type :',0 RAM_TYPE_2 db 'Bank4/5 DRAM Type :',0 endif; Ocean_SPECIAL_DRAM_TYPE endif; SPECIAL_DRAM_TYPE_2 endif; SPECIAL_DRAM_TYPE EDO_RAM db 'EDO',0 ifdef SUPPORT_SDRAM_II SDRAM_II_RAM db 'SDRAM II',0 endif; SUPPORT_SDRAM_II S_DRAM db 'Sync. DRAM',0 NORMAL_RAM db 'Fast Page',0 endif; NEW_DRAM_TYPE_SHOW ;R34 SRAM_TYPE db 'L2 Cache Type :',0 ;R34 P_BURST_TYPE db 'Pipeline',0 NONE_TYPE db 'None',0 X_Ct_Show_Config proc far push cs pop ds mov al,BYTE PTR CURSOR_X[bp] mov ah,BYTE PTR CURSOR_Y[bp] push ax mov BYTE PTR CURSOR_X[bp],42 mov BYTE PTR CURSOR_Y[bp],10 mov si,offset RAM_TYPE_0 call X_Display_String mov BYTE PTR CURSOR_X[bp],42 mov BYTE PTR CURSOR_Y[bp],11 mov si,offset RAM_TYPE_1 call X_Display_String mov BYTE PTR CURSOR_X[bp],42 mov BYTE PTR CURSOR_Y[bp],12 ifdef NEW_DRAM_TYPE_SHOW ifdef Show_Cache_Type mov si,offset SRAM_TYPE call X_Display_String endif; Show_Cache_Type else; NEW_DRAM_TYPE_SHOW mov si,offset RAM_TYPE_2 call X_Display_String ifdef Show_Cache_Type mov BYTE PTR CURSOR_X[bp],2 mov BYTE PTR CURSOR_Y[bp],14 mov si,offset SRAM_TYPE call X_Display_String endif; Show_Cache_Type endif; NEW_DRAM_TYPE_SHOW ifdef NEW_DRAM_TYPE_SHOW ;---------------; ; LOCATE 10,62 ; ;---------------; mov BYTE PTR CURSOR_X[bp],62 mov BYTE PTR CURSOR_Y[bp],10 ;---------------; ; Get DRAM Type ; ;---------------; mov cx,VT692+60h call X_Get_ct mov bl, al ; Save DRAM Type Value ;-------------------------------; ; Show EDO DRAM at Bank ? ; ;-------------------------------; xor bh, bh ; Clear Flag and al,03h cmp al,01h jnz short Bank_0_No_EDO or bh,1 ; Set Flag bit 0 IFDEF DRAM_Bank_Show_As_SIMM ;R05A - starts mov si,offset BANK0 call X_Display_String push bx mov cx,VT692+5Ah call X_Get_ct mov bl,al mov cx,VT692+5Bh call X_Get_ct sub al,bl pop bx jz short @F mov si,offset BANK1 call X_Display_String @@: ELSE; DRAM_Bank_Show_As_SIMM ;R05A - ends mov si,offset BANK0 call X_Display_String ENDIF; DRAM_Bank_Show_As_SIMM ;R05A Bank_0_No_EDO: mov al,bl and al,0Ch cmp al,04h jnz short Bank_1_No_EDO or bh,2 ; Set Flag bit 1 IFDEF DRAM_Bank_Show_As_SIMM ;R05A - starts mov si,offset BANK2 call X_Display_String push bx mov cx,VT692+5Ch call X_Get_ct mov bl,al mov cx,VT692+5Dh call X_Get_ct sub al,bl pop bx jz short @F mov si,offset BANK3 call X_Display_String @@: ELSE; DRAM_Bank_Show_As_SIMM ;R05A - ends mov si,offset BANK1 call X_Display_String ENDIF; DRAM_Bank_Show_As_SIMM ;R05A Bank_1_No_EDO: mov al,bl and al,30h cmp al,10h jnz short Bank_2_No_EDO or bh,4 ; Set Flag bit 2 IFDEF DRAM_Bank_Show_As_SIMM ;R05A - starts mov si,offset BANK4 call X_Display_String push bx mov cx,VT692+5Eh call X_Get_ct mov bl,al mov cx,VT692+5Fh call X_Get_ct sub al,bl pop bx jz short @F mov si,offset BANK5 call X_Display_String @@: ELSE; DRAM_Bank_Show_As_SIMM ;R05A - ends mov si,offset BANK2 call X_Display_String ENDIF; DRAM_Bank_Show_As_SIMM ;R05A Bank_2_No_EDO: mov al,bl and al,0c0h cmp al,40h jnz short Bank_3_No_EDO or bh,8 ; Set Flag bit 3 IFDEF DRAM_Bank_Show_As_SIMM ;R05A - starts mov si,offset BANK6 call X_Display_String push bx mov cx,VT692+56h call X_Get_ct mov bl,al mov cx,VT692+57h call X_Get_ct sub al,bl pop bx jz short @F mov si,offset BANK7 call X_Display_String @@: ELSE; DRAM_Bank_Show_As_SIMM ;R05A - ends mov si,offset BANK3 call X_Display_String ENDIF; DRAM_Bank_Show_As_SIMM ;R05A Bank_3_No_EDO: or bh, bh ; Test Flag jnz short Have_EDO mov si,offset NONE_TYPE call X_Display_String Have_EDO: ;---------------; ; LOCATE 10,62 ; ;---------------; mov BYTE PTR CURSOR_X[bp],62 mov BYTE PTR CURSOR_Y[bp],11 xor bh, bh ; Clear Flag ;-------------------------------; ; Show SDRAM at Bank ? ; ;-------------------------------; mov al, bl and al,03h cmp al,03h jnz short Bank_0_No_SDRAM or bh,1 ; Set Flag bit 0 IFDEF DRAM_Bank_Show_As_SIMM ;R05A - starts mov si,offset BANK0 call X_Display_String push bx mov cx,VT692+5Ah call X_Get_ct mov bl,al mov cx,VT692+5Bh call X_Get_ct sub al,bl pop bx jz short @F mov si,offset BANK1 call X_Display_String @@: ELSE; DRAM_Bank_Show_As_SIMM ;R05A - ends mov si,offset BANK0 call X_Display_String ENDIF; DRAM_Bank_Show_As_SIMM ;R05A Bank_0_No_SDRAM: mov al,bl and al,0Ch cmp al,0Ch jnz short Bank_1_No_SDRAM or bh,2 ; Set Flag bit 1 IFDEF DRAM_Bank_Show_As_SIMM ;R05A - starts mov si,offset BANK2 call X_Display_String push bx mov cx,VT692+5Ch call X_Get_ct mov bl,al mov cx,VT692+5Dh call X_Get_ct sub al,bl pop bx jz short @F mov si,offset BANK3 call X_Display_String @@: ELSE; DRAM_Bank_Show_As_SIMM ;R05A - ends mov si,offset BANK1 call X_Display_String ENDIF; DRAM_Bank_Show_As_SIMM ;R05A Bank_1_No_SDRAM: mov al,bl and al,30h cmp al,30h jnz short Bank_2_No_SDRAM or bh,4 ; Set Flag bit 2 IFDEF DRAM_Bank_Show_As_SIMM ;R05A - starts mov si,offset BANK4 call X_Display_String push bx mov cx,VT692+5Eh call X_Get_ct mov bl,al mov cx,VT692+5Fh call X_Get_ct sub al,bl pop bx jz short @F mov si,offset BANK5 call X_Display_String @@: ELSE; DRAM_Bank_Show_As_SIMM ;R05A - ends mov si,offset BANK2 call X_Display_String ENDIF; DRAM_Bank_Show_As_SIMM ;R05A Bank_2_No_SDRAM: mov al,bl and al,0c0h cmp al,0c0h jnz short Bank_3_No_SDRAM or bh,8 ; Set Flag bit 2 IFDEF DRAM_Bank_Show_As_SIMM ;R05A - starts mov si,offset BANK6 call X_Display_String push bx mov cx,VT692+56h call X_Get_ct mov bl,al mov cx,VT692+57h call X_Get_ct sub al,bl pop bx jz short @F mov si,offset BANK7 call X_Display_String @@: ELSE; DRAM_Bank_Show_As_SIMM ;R05A - ends mov si,offset BANK3 call X_Display_String ENDIF; DRAM_Bank_Show_As_SIMM ;R05A Bank_3_No_SDRAM: or bh, bh ; Test Flag jnz short Have_SDRAM mov si,offset NONE_TYPE call X_Display_String Have_SDRAM: ;R34 - starts IFDEF SHOW_ECC_FUNC mov BYTE PTR CURSOR_X[bp],42 mov BYTE PTR CURSOR_Y[bp],12 mov si,offset ECC_TITLE call X_Display_String ;-------------------------------; ; Test Every Bank DRAM exist ? ; ;-------------------------------; xor bx,bx ; bit of bl means bank exist ? mov cx, VT692 + 5bh Check_Bank_Exist: shr bl,1 call X_Get_Ct cmp al,bh mov bh, al jz short Next_Bank or bl, 8h ; Bank is exist Next_Bank: add cx,2 cmp cx,VT692 + 59h je short Check_Bank_Exist_End cmp cx,VT692 + 61h jne Not_Bank_67 mov cx,VT692 + 57h Not_Bank_67: jmp short Check_Bank_Exist Check_Bank_Exist_End: ; bit of bl means bank exist ? ; bit 0 : bank 0/1 (1:exist) ; bit 1 : bank 2/3 (0:none ) ; bit 2 : bank 4/5 ; bit 3 : bank 6/7 ;-------------------------------; ; Test ECC DRAM exist & Enable ?; ;-------------------------------; mov cx,VT692+6Eh call X_Get_ct and al,bl mov si,offset ECC_DIS_VAL jz short show_no_ecc mov si,offset ECC_EN_VAL show_no_ecc: mov BYTE PTR CURSOR_X[bp],62 mov BYTE PTR CURSOR_Y[bp],12 call X_Display_String ENDIF; SHOW_ECC_FUNC ;R34 - ends ;---------------; ; END ! ; ;---------------; else; NEW_DRAM_TYPE_SHOW mov bx, 1 mov cx, VT692+5bh xor dx, dx plugged_dram: push dx call X_Get_Ct pop dx mov dh, al sub al, dl jz short @F or bh, bl @@: xchg dh, dl shl bl, 1 add cl, 2 cmp cl, 60h jb short plugged_dram mov cx, VT692+57h push dx call X_Get_Ct pop dx sub al, dl jz short @f or bh, bl ;;BH = plugged DRAM bit map mov cx,VT692+60h call X_Get_ct mov cl,2 xor di,di mov ch, bh mov bx,ax GET_DRAM: mov si,offset NONE_TYPE test ch, 1 jz DRAM_OK and al,3 mov si,offset NORMAL_RAM jz short DRAM_OK ;;it's fast page cmp al,3 mov si,offset S_DRAM je short DRAM_OK ;;it's Sync. DRAM ifdef SUPPORT_SDRAM_II and al,1 mov si,offset EDO_RAM jnz short DRAM_OK ;;it's EDO mov si,offset SDRAM_II_RAM ;;No, it's SDRAM II else; SUPPORT_SDRAM_II mov si,offset EDO_RAM endif; SUPPORT_SDRAM_II DRAM_OK: mov BYTE PTR CURSOR_X[bp],62 cmp di,1 je short DRAM2 cmp di,2 je short DRAM3 cmp di, 3 je short DRAM4 ifdef Change_DIMM1_2_Show mov BYTE PTR CURSOR_Y[bp],11 else; Change_DIMM1_2_Show mov BYTE PTR CURSOR_Y[bp],10 endif; Change_DIMM1_2_Show call X_Display_String inc di shr ch, 1 mov ax,bx shr al,cl jmp short GET_DRAM DRAM2: ifdef Change_DIMM1_2_Show mov BYTE PTR CURSOR_Y[bp],10 else; Change_DIMM1_2_Show mov BYTE PTR CURSOR_Y[bp],11 endif; Change_DIMM1_2_Show call X_Display_String add cl,2 inc di shr ch, 1 mov ax,bx shr al,cl jmp short GET_DRAM DRAM3: mov BYTE PTR CURSOR_Y[bp],12 call X_Display_String add cl,2 inc di shr ch, 1 mov ax,bx shr al,cl jmp short GET_DRAM DRAM4: mov BYTE PTR CURSOR_Y[bp],13 call X_Display_String endif; NEW_DRAM_TYPE_SHOW pop ax mov BYTE PTR CURSOR_X[bp],al mov BYTE PTR CURSOR_Y[bp],ah ;R24 - start ifdef GPO_LOW_BEFORE_BOOT mov bl,GPO_LOW_BEFORE_BOOT post_func_call E000_GPO_PIN_LOW endif; GPO_LOW_BEFORE_BOOT ifdef GPO_HIGH_BEFORE_BOOT mov bl,GPO_HIGH_BEFORE_BOOT post_func_call E000_GPO_PIN_High endif; GPO_HIGH_BEFORE_BOOT ;R24 - end ret X_Ct_Show_Config endp ;[]==============================================================[] ;X_Init_Onboard_Io: (POST 32h) ; Initial onboard I/O chip ;Save : all but flags ;Input : none ;Output: none ;Note : 1. This routine will be called before I/O installation. ; 2. This is a customerization routine if you need. ;[]==============================================================[] X_Init_Onboard_Io proc Far ifndef No_SDRAM_Load_Default ;R12 - starts IFNDEF Clear_SDRAM_Load_D4_In_POST0E ;-----------------------------------------------; ; Reset the Status of SDRAM_Load_Default ; ;-----------------------------------------------; IFNDEF SDRAM_Load_Default_CMOS mov al, [bp]+ 37h and al, not (03h) or al, ((03h shl 1) and (03h)) mov [bp]+37h, al ELSE; SDRAM_Load_Default_CMOS mov al, [bp]+ SDRAM_Load_Default_CMOS and al, not (SDRAM_Load_Default_Bit) or al, ((SDRAM_Load_Default_Bit shl 1) and (SDRAM_Load_Default_Bit)) mov [bp]+SDRAM_Load_Default_CMOS, al ENDIF; SDRAM_Load_Default_CMOS ENDIF; Clear_SDRAM_Load_D4_In_POST0E endif ;No_SDRAM_Load_Default ;R12 - ends ;---------------; ; Memory Hole ; ;---------------; ;At this moment , the memory has sized & tested. If memory hole is needed, ;Program chipset registers and modify extended memory here. ;The extended memory size found is in both EXT_MEM_FOUND[bp] & EXT_MEMORY[bp] ;location. mov si,offset Mem_Hole_Item call X_GetItem_Value test al,00000010b ;memory hole enabled? jz No_Memory_Hole cmp al,2 jne short @F ;set non-cacheable region at F00000-FFFFFF mov cx,VT692 + 55h mov al,07h call X_Set_Ct mov cx,VT692 + 54h mov al,85h ;set non-cacheable top call X_Set_Ct mov cx,VT692 + 63h mov bx, 08F3h ;set non-cacheable range call X_Get_Set_Ct mov eax,14*1024 ;memory hole xor ebx,ebx mov bx,EXT_MEM_FOUND[bp] cmp eax,ebx ;memory hole is bigger than jae No_Mem_Modify ;extended memory size mov EXT_MEM_FOUND[bp],ax ;modify memory size mov EXT_MEMORY[bp],ax ;modify memory size jmp No_Memory_Hole @@: cmp al,3 jne short No_Memory_Hole ;set non-cacheable region at E00000-FFFFFF mov cx,VT692 + 55h mov al,07h call X_Set_Ct mov cx,VT692 + 54h mov al,06h ;set non-cacheable top call X_Set_Ct mov cx,VT692 + 63h mov bx, 0CF3h ;set non-cacheable range call X_Get_Set_Ct mov eax,13*1024 ;memory hole xor ebx,ebx mov bx,EXT_MEM_FOUND[bp] cmp eax,ebx ;memory hole is bigger than jae No_Mem_Modify ;extended memory size mov EXT_MEM_FOUND[bp],ax ;modify memory size mov EXT_MEMORY[bp],ax ;modify memory size @@: No_Memory_Hole: No_Mem_Modify: ;---------------; ; IDE Prefetch ; ;---------------; mov si,offset IDE_PF_Item call X_GetItem_Value xor bh, bh or al, al jz short @F ifdef Disable_IDEPreFetch_When_75MHz post_func_call Look_For_75MHz ; If 75MHz => jc short @f ; Disable IDE Prefetch. endif; Disable_IDEPreFetch_When_75MHz mov bh, 0E0h @@: mov cx, VT586_IDE+41h mov bl, 0Fh call X_Get_Set_Ct ifdef Jumpless_Support post_func_call Update_Jumpless_Screen endif; Jumpless_Support clc ret X_Init_Onboard_Io endp ;[]=============================================================[] ;Procedure : X_Ct_OnChip_IDE_Chk (POST 0Bh)(call from Pci_IO_Mem_Init) ;Function : Return status of On-chip IDE for PCI add-in PCI/IDE ; controlling ; ;Input : none ; ;Output : carry set - OnChip IDE disabled ; no carry - Onchip IDE enabled ;Note : This function should return right status of on-chip ; IDE, otherwise IDE port will be conflicted if ; PCI/IDE card is plugged ;[]=============================================================[] X_Ct_OnChip_IDE_Chk proc Far pusha ifndef VT596 ;-----------------------------------------------; ; Patch 586B(3041) 44,45,46 Revision about IDE ; ;-----------------------------------------------; mov cx, VT586 + 08h ; Check Revision call X_Get_Ct cmp al,46h ; If 46h ? jnz short End_IDE_Patch_ mov cx, VT586_IDE + 44h ; IDE RX44<2> = 1 mov bl,04h ; call X_Get_Set_Ct_OR ; jmp short IDE_Threshold_Exit ; End_IDE_Patch_: endif; VT596 ifdef Ultra_DMA33_support IFDEF Have_IDE_Threshold_Item mov si,offset IDE_Threshold_Item call X_GetItem_Value or al,al jz short Disable_IDE_Threshold ENDIF;Have_IDE_Threshold_Item mov cx,VT586_IDE+45h ; Set Channel0/1 UltraDMA mov bl,03h ; (Set IDE Threshold Enable) call X_Get_Set_Ct_OR IFDEF Have_IDE_Threshold_Item jmp short IDE_Threshold_Exit Disable_IDE_Threshold: mov cx,VT586_IDE+43h ; Enable => Reg43[7](0:Enable) mov bl,not 80h ; "Clear DMA Write Flag by call X_Get_Set_Ct_AND ; IO Write to Port 1F7/177" ENDIF;Have_IDE_Threshold_Item IDE_Threshold_Exit: endif ;Ultra_DMA33_support ;---------------------------------------; ; Check OnChip IDE Disabled/Enable ? ; ;---------------------------------------; mov si,offset ONBD_1IDE_Item call X_GetItem_Value or al,al ;on chip IDE enabled? stc ;assume disabled jz short OnChipIde_Disabled clc OnChipIde_Disabled: popa ret X_Ct_OnChip_IDE_Chk endp ;[]=============================================================[] ; X_Ct_MemHole_Status: ;Function : return memory hole at 15Mb-16Mb status ; ;Input : none ;Output : AL - 0 = hole disabled ; 1 = hole enabled ;[]=============================================================[] X_Ct_MemHole_Status proc Far mov si,offset Mem_Hole_Item call X_GetItem_Value ret X_Ct_MemHole_Status endp ;[]==============================================================[] ;X_CACHE_INIT: (POST 09h) ; Cache controller initialization after first testing ; first 64k memory. ;Saves: ALL but flags ;Input: none ;Output:none ; ;[Notes] 1. Stack is available ; 2. This function can be used to sizing cache size ;[]==============================================================[] X_Cache_Init proc far ;R48 - start ifdef MP_SUPPORT mov cx, VT596 + 074h ifdef USE_EXTERNAL_IOAPIC ;R48A mov bl, 080h ;enable external IOAPIC ;R48A else; USE_EXTERNAL_IOAPIC ;R48A mov bl, 02h ;enable interal IOAPIC endif; USE_EXTERNAL_IOAPIC ;R48A call X_Get_Set_Ct_OR ; endif; MP_SUPPORT ;R48 - end xor al,al ; force A20 low in 92h port out 92h,al NEWIODELAY ret X_Cache_Init endp ;R13 - starts X_Later_Cache_Sizing Proc Far IF ((NOT RTC_PS2_KBC) AND 02h) ifndef No_Cut_IRQ12_When_No_PS2_Pluged ;R13A push ds push 0f000h pop ds ;---------------------------------------; ; Set MDATA to IRQ12 for ISA device ; ; if PS2 mouse not installed ; ;---------------------------------------; extrn SYSTEM1_BYTE:BYTE test byte ptr ds:[SYSTEM1_BYTE], 04H ;PS2 existed ? jnz short PS2_Mouse_Is_Present mov cx, VT586 + 05Ah ;Release IRQ12 mov bl, 02h ; call X_Get_Set_Ct_OR ; PS2_Mouse_Is_Present: pop ds endif; No_Cut_IRQ12_When_No_PS2_Pluged ;R13A ENDIF; ((NOT RTC_PS2_KBC) AND 02h) ret X_Later_Cache_Sizing Endp ;R13 - ends XCODE ENDS ;************************************************************** ;************************************************************** ;***** The following codes will be located at E000 ! ********** ;***** The following codes will be located at E000 ! ********** ;***** The following codes will be located at E000 ! ********** ;***** The following codes will be located at E000 ! ********** ;************************************************************** ;************************************************************** EGROUP GROUP ECODE ECODE SEGMENT USE16 PARA PUBLIC 'ECODE' ASSUME CS:EGROUP,DS:G_RAM,ES:EGROUP ;R14 - starts ifdef SMBus_Port ;R14A public Ct_I2CReadByte public Ct_I2CWriteByte public Ct_I2CReadWord public Ct_I2CWriteWord public Ct_Chk_SMBus_READY extrn WaitSMBus:near ;[]==============================================================[] ;Input : CL - register index ; CH - device ID ;Output : AL - Value read ;[]==============================================================[] Ct_I2CReadByte Proc Near push cx mov dx,SMBus_Port +04h inc ch mov al,ch ;ID cmd(read) out dx,al NEWIODELAY NEWIODELAY call Ct_Chk_SMBus_READY pop ax mov dl,03h out dx,al ;Index NEWIODELAY NEWIODELAY mov dl,02h mov al,48h out dx,al ;read data NEWIODELAY NEWIODELAY mov cx,1000h @@: newiodelay loop short @B call Ct_Chk_SMBus_READY mov dl,05 in al,dx ;Data0 NEWIODELAY NEWIODELAY ret Ct_I2CReadByte Endp ;[]==============================================================[] ;Input : CL - register index ; CH - device ID ; AL - Value to write ;Output: none ;[]==============================================================[] Ct_I2CWriteByte Proc Near push ax push cx mov dx,SMBus_Port +04h mov al,ch ;ID cmd(Write) out dx,al NEWIODELAY NEWIODELAY call Ct_Chk_SMBus_READY pop ax mov dl,03h out dx,al ;Index NEWIODELAY NEWIODELAY pop ax mov dl,05 out dx,al ;Data0 NEWIODELAY NEWIODELAY mov dl,02h mov al,48h out dx,al ;write data NEWIODELAY NEWIODELAY mov cx,1000h @@: newiodelay loop short @B call Ct_Chk_SMBus_READY ret Ct_I2CWriteByte Endp ;[]==============================================================[] ;Input : CL - register index ; CH - device ID ;Output : AX - Value read ;[]==============================================================[] Ct_I2CReadWord Proc Near push cx mov dx,SMBus_Port +04h inc ch mov al,ch ;ID cmd(read) out dx,al NEWIODELAY NEWIODELAY call Ct_Chk_SMBus_READY mov dl,03h pop ax out dx,al ;Index NEWIODELAY NEWIODELAY mov dl,02h mov al,4ch out dx,al ;write data NEWIODELAY NEWIODELAY xor cx,cx @@: newiodelay loop short @B call Ct_Chk_SMBus_READY mov dl,06 in al,dx ;Data1 NEWIODELAY NEWIODELAY mov ah,al mov dl,05 in al,dx ;Data0 NEWIODELAY NEWIODELAY ret Ct_I2CReadWord endp ;[]==============================================================[] ;Input : CL - register index ; CH - device ID ; AX - Value to write ;Output: none ;[]==============================================================[] Ct_I2CWriteWord Proc Near push ax push cx mov dx,SMBus_Port +04h mov al,ch ;ID cmd(Write) out dx,al NEWIODELAY NEWIODELAY call Ct_Chk_SMBus_READY pop ax mov dl,03h out dx,al ;Index NEWIODELAY NEWIODELAY pop ax mov dl,05 out dx,al ;Data0 NEWIODELAY NEWIODELAY mov dl,06 mov al,ah out dx,al ;Data1 NEWIODELAY NEWIODELAY mov dl,02h mov al,4ch out dx,al ;write data NEWIODELAY NEWIODELAY xor cx,cx @@: newiodelay loop short @B call Ct_Chk_SMBus_READY ret Ct_I2CWriteWord Endp Ct_Chk_SMBus_READY Proc Near mov dx,SMBus_Port + 0 clc mov cx,0100h Chk_I2C_OK: in al,dx ;get status or al,al jz short Clear_final test al,04h jnz short SMBus_Err test al,01h ;busy ? jz short Not_Smbusy call WaitSmbus Not_Smbusy: out dx,al loop short Chk_I2C_OK SMBus_Err: out dx,al NEWIODELAY in al,dx ;get status NEWIODELAY test al,04h jnz short SMBus_Err stc Clear_final: ret Ct_Chk_SMBus_READY Endp endif; SMBus_Port ;R14A ;R14 - ends ifdef SMBus_Port Public Ct_Get_Row_Map Ct_Get_Row_Map Proc Near xcall X_Ct_Get_Row_Map ret Ct_Get_Row_Map Endp endif; SMBus_Port ifndef No_SDRAM_Load_Default ;R12 - starts IFDEF OEM_Error_Special_Show2 public OEM_Error_Special_String2 OEM_Error_Special_String2 db 'Warning: PowerOn three times fail!' db ' Please entry SETUP to ' db 'slow down DRAM Timing.',0 ENDIF;OEM_Error_Special_Show2 endif ;No_SDRAM_Load_Default ;R12 - ends ;R26 - starts Halt_System_IF_NOVGA Proc Far push ds mov ax, 0C000h mov ds, ax cmp word ptr ds:[0],0AA55h je short V_BIOS_Found mov bl,1 extrn Snd_Spkr:near F000_call DGROUP:Snd_Spkr jmp $ V_BIOS_Found: pop ds ret Halt_System_IF_NOVGA Endp ;R26 - ends ;[]==============================================================[] ;E000_CT_REMAP: (POST 30h) ; Remap unused memory from 640k to 1M ;Saves: all but flags ;Input: none ;Output:none ;[Notes] 1. Program chipset register if remap allowed. ;[]==============================================================[] E000_Ct_Remap proc far IFDEF WAKE_LAN_BY_LID ;R09 mov cl, 03h ;R09 Enable Power Buttom mov bl, 01h ;R09 call E000_Get_Set_PMIO_OR ;R09 ENDIF;WAKE_LAN_BY_LID ;R09 IFDEF PATCH_WOL_STATUS ;R09 mov cl, 03h ;R09 Enable Power Buttom mov bl, 01h ;R09 call E000_Get_Set_PMIO_OR ;R09 ENDIF;PATCH_WOL_STATUS ;R09 ;---------------------------------------; ; Re-Indicat CPU(Host) CLK Table ; ;---------------------------------------; call Ct_Quatify_100Mhz ; If 100MHz Host CLK ? jnc short Not_100MHz_HCLK ; Not, Jmp push es ; Re-Indicat CPU(Host) CLK assume es:G_RAM ; to 100MHz. mov ax,G_RAM mov es, ax mov si, offset CPU_CLOCK and byte ptr es:[si],not CPU_CLOCK_MASK or byte ptr es:[si],CPU100 pop es Not_100MHz_HCLK: ;R33 - start ifdef Issue_Gemlight_TV_Out_Function pushad push es push ds push seg dgroup pop ds mov si,offset TV_Out_Mode_Item pop ds call F000_GetItem_Value test al,01h ;PAL system jz short NSTL_System mov ax,0c000h mov es,ax mov di,0048h mov di,word ptr es:[di] add di,0030h mov bh,byte ptr es:[di] and bh,0f0h or bl,bh mov byte ptr es:[di],bl NSTL_System: pop es popad endif; Issue_Gemlight_TV_Out_Function ;R33 - end ret E000_Ct_Remap endp ;[]=============================================================[] ; Inputs: None ; Output: CF: 100 Mhz ; NC: 66 Mhz ;[]=============================================================[] public Ct_Quatify_100Mhz Ct_Quatify_100Mhz proc near mov cx,VT692 + 68h call _Get_Ct test al,01h ; If 100MHz Host CLK ? jz short C_Not_100MHz_HCLK ; Not, Jmp stc ;100 Mhz ret C_Not_100MHz_HCLK: clc ;66 Mhz ret Ct_Quatify_100Mhz endp ;[]==============================================================[] ; _get_ct(Get_PCI): ; Reads a value directly from the chipset register. ; ; Input : CX = Index register to read ; Output : AL = Value read ; Destory: EAX, DX ;[]==============================================================[] Public _get_ct _get_ct proc near F000_call Get_Ct ret _get_ct endp ;[]==============================================================[] ; _set_ct(Set_PCI): ; Changes a value in the chipset register. ; Input : CX = Index register to change ; AL = Value to change ; Output : None ; Destory: EAX, ECX, DX ; ;[]==============================================================[] Public _set_ct _set_ct proc near push cx ;R29 F000_call Set_Ct pop cx ;R29 ret _set_ct endp ;[]==============================================================[] ; _get_set_ct(Get_Set_PCI): ; Changes a value in the chipset register. ; Input : CX = Index register to change ; bx = Value to change ; Output : None ; Destory: EAX, ECX, DX ; ;[]==============================================================[] Public _Get_Set_Ct _Get_set_ct proc near ;R29 F000_call Get_Set_Ct call _Get_Ct ;R29 and al, bl ;R29 AND data or al, bh ;R29 OR data call _Set_Ct ;R29 ret _Get_set_ct endp ;[]==============================================================[] ; _Get_Set_Ct_OR(Get_Set_PCI_OR): ; Changes a value in the chipset register. ; Input : CX = Index register to change ; bl = Value to change (OR) ; Output : None ; Destory: EAX, ECX, DX ; ;[]==============================================================[] Public _Get_Set_Ct_OR _Get_Set_Ct_OR proc near call _Get_Ct or al, bl ;OR data call _Set_Ct ret _Get_Set_Ct_OR endp ;[]==============================================================[] ; _Get_Set_Ct_AND(Get_Set_PCI_AND): ; Changes a value in the chipset register. ; Input : CX = Index register to change. ; bl = Value to change (AND) ; Output : None ; Destory: EAX, ECX, DX ; ;[]==============================================================[] Public _Get_Set_Ct_AND _Get_Set_Ct_AND proc near call _Get_Ct and al, bl ;AND data call _Set_Ct ret _Get_Set_Ct_AND endp ;[]==============================================================[] ; _Set_Ct_Clear(_Set_PCI_Clear): ; Clear a value in the chipset register. ; Input : CX = Index register to change. ; Output : None ; Destory: EAX, ECX, DX ; ;[]==============================================================[] Public _Set_Ct_Clear _Set_Ct_Clear proc near xor al,al ; Zero call _Set_Ct ; Clear ret _Set_Ct_Clear endp ;[]==============================================================[] ; _get_PMIO: ; Reads a value directly from the chipset register. ; ; Input : CX = Index value of IO port ; Output : AL = Value read ; Destory: EAX ;[]==============================================================[] Public _Get_PMIO _Get_PMIO proc near F000_call Get_PMIO ret _Get_PMIO endp ;[]==============================================================[] ; _set_pmio: ; Changes a value in the chipset register. ; Input : CX = Index port to change ; AL = Value to change ; Output : None ; Destory: EAX ; ;[]==============================================================[] Public _Set_PMIO _Set_PMIO proc near F000_call Set_PMIO ret _Set_PMIO endp Public F000_Get_Cmos2 F000_Get_Cmos2 Proc Near F000_Call Get_Cmos2 ret F000_Get_Cmos2 Endp Public F000_Set_Cmos2 F000_Set_Cmos2 Proc Near F000_Call Set_Cmos2 ret F000_Set_Cmos2 Endp ;[]==============================================================[] ; ; E000_Ct_Early_Shadow: (POST 0Bh) ; ; Shadowing system and video BIOS to speedup booting. ; ;Saves: ; ; All except ax,dx,es,ds,flag ;Input : None ;Output: None ; ;[Notes] ; ; 1. This routine will shadow system BIOS in early stage ; of POST. ; 2. Stack available ;[]==============================================================[] E000_Ct_Early_Shadow proc far ;R49 start ifdef Patch_3COM_LANCard_Boot pushad xor bx,bx scanPci: push ecx mov cl,0Ah ; read class code Call F000_Get_CfgSpace_Word pop ecx inc ax jnz short pciCardFound ; Treat if it was not -1 nextDevice: add cx,0800h jc short notfound ; no lan card found jmp short scanPci pciCardFound: mov cl, 14h ; read Cap_ptr register cmp ax, 0608h ; Is it Cardbus Bridge? (+1) jz short cardBusBridgeFound mov cl, 34h ; read Cap_ptr register cardBusBridgeFound: push ecx mov cl,06h Call F000_Get_CfgSpace_DWord test al, 10h ; Bit 4 (Capabilities bit) set ? pop ecx jz short nextdevice ; If not (PCI PME support?) Call F000_Get_CfgSpace_Word cmp al, 40h ; Capabilities list offset jb short nextdevice mov cl, al ; Capabilities list offset nextItem: Call F000_Get_CfgSpace_DWord cmp al, 1 ; Cap_ID ? jz short foundCap_ID cmp ah, 0 ; Last item? jz short nextdevice ; If last item mov cl, ah jmp short nextItem foundCap_ID: bt eax, 21 ; Device Specific Initialisation ? jc short nextdevice ; If yes add cl, 4 ; PMCSR offset Call F000_Get_CfgSpace_Word or ah, 81h ; Clear PME_Status and PME_En and al, 0fch ; PowerState = D0 Call F000_Set_CfgSpace_Word jmp short nextdevice notfound: popad endif ;Patch_3COM_LANCard_Boot ;R49 end ifdef VIA686AIO ;R43 - starts push es ASSUME es:G_RAM mov ax,G_RAM mov es,ax mov si, offset Sound_Blaster_Item call F000_Getitem_Value or al,al jz short Legacy_SB_Disabled mov si, offset SB_IRQ_Item call F000_Getitem_Value mov si,offset SB_IRQ_Item_TBL shl al,1 xor ah,ah add si,ax mov ax,word ptr cs:[si] not ax and word ptr es:[IRQ_MAP],ax Legacy_SB_Disabled: pop es endif; VIA686AIO ;R43 - ends ;Read on-chip IDE controller PCI device ID and enable/disable it with setup ;selection, the device ID of on-chip IDE will strapped from hardware jumper ;read device ID of on-chip IDE mov si, offset ONBD_1IDE_Item call F000_Getitem_Value shl al, 1 mov bh, al ifndef ONCHIP_2ND_ALWAYS_DISABLE extrn ONBD_2IDE_Item:near mov si, offset ONBD_2IDE_Item call F000_Getitem_Value or bh, al endif; ONCHIP_2ND_ALWAYS_DISABLE mov cx,VT586_IDE + 40h call _Get_Ct mov bl,NOT 03H ;mask bits call _Get_Set_Ct mov cx,VT586_IDE + 09h mov bx, 0AF0h ;mask bits call _Get_Set_Ct @@: ifdef VT692_PP ;-----------------------; ; Aperture Size ; ;-----------------------; mov si,offset Aperture_Size_Item call F000_Getitem_Value cmp al,0 jne short Size_128 xor bl,bl ;256M jmp short Set_Size Size_128: cmp al,1 jne short Size_64 mov bl,80h ;128M jmp short Set_Size Size_64: cmp al,2 jne short Size_32 mov bl,0c0h ;64M jmp short Set_Size Size_32: cmp al,3 jne short Size_16 mov bl,0e0h ;32M jmp short Set_Size Size_16: cmp al,4 jne short Size_8 mov bl,0f0h ;16M jmp short Set_Size Size_8: cmp al,5 jne short Size_4 mov bl,0f8h ;8M jmp short Set_Size Size_4: mov bl,0fch ;4M Set_Size: mov cx, VT692+84h mov al,bl call _Set_Ct mov cx, VT692+88h ; Enable AGP mov bl, 02h call _Get_Set_Ct_OR endif; VT692_PP ;-----------------------------------------------; ; Special Control OnBoard Chip (Ex: Audio) ; ;-----------------------------------------------; ifndef VT596 IFDEF Control_Onchip_By_GPIO_Low mov cl, 40h ; Set GPIO to Output mov bl, Control_Onchip_By_GPIO_Low call E000_Get_Set_PMIO_OR ; mov cl, 42h ; Enable Onboard Chip ; (Special Control by GPIO) mov bl,not Control_Onchip_By_GPIO_Low call E000_Get_Set_PMIO_AND ; Set GPIO to Low mov si, offset ONBD_Chip_Item call F000_Getitem_Value or al, al jnz short @f mov cl, 42h ; Disable Onboard Chip ; (Special Control by GPIO) mov bl, Control_Onchip_By_GPIO_Low call E000_Get_Set_PMIO_OR ; Set GPIO to High @@: ENDIF;Control_Onchip_By_GPIO_Low endif; VT596 ifdef VT596 IFDEF Control_Onchip_By_GPO_Low mov si, offset ONBD_Chip_Item call F000_Getitem_Value xor al,1 mov bh,al if Control_Onchip_By_GPO_Low LE 7 shl bh,(Control_Onchip_By_GPO_Low) mov bl,0FEh rol bl,(Control_Onchip_By_GPO_Low) mov cl, 4ch ; Set Onboard Chip En/Disable ; (Special Control by GPIO) call E000_Get_Set_PMIO ; Low=>Enable ,High=>Disable endif;Control_Onchip_By_GPO_Low LE 7 if Control_Onchip_By_GPO_Low LE 15 if Control_Onchip_By_GPO_Low LE 8 shl bh,(Control_Onchip_By_GPO_Low - 8) mov bl,0FEh rol bl,(Control_Onchip_By_GPO_Low - 8) mov cl, 4dh ; Set Onboard Chip En/Disable ; (Special Control by GPIO) call E000_Get_Set_PMIO ; Low=>Enable ,High=>Disable endif;Control_Onchip_By_GPO_Low GE 8 endif;Control_Onchip_By_GPO_Low LE 15 if Control_Onchip_By_GPO_Low LE 23 if Control_Onchip_By_GPO_Low LE 16 shl bh,(Control_Onchip_By_GPO_Low - 16) mov bl,0FEh rol bl,(Control_Onchip_By_GPO_Low - 16) mov cl, 4eh ; Set Onboard Chip En/Disable ; (Special Control by GPIO) call E000_Get_Set_PMIO ; Low=>Enable ,High=>Disable endif;Control_Onchip_By_GPO_Low GE 16 endif;Control_Onchip_By_GPO_Low LE 23 if Control_Onchip_By_GPO_Low LE 30 if Control_Onchip_By_GPO_Low LE 24 shl bh,(Control_Onchip_By_GPO_Low - 24) mov bl,0FEh rol bl,(Control_Onchip_By_GPO_Low - 24) mov cl, 4fh ; Set Onboard Chip En/Disable ; (Special Control by GPIO) call E000_Get_Set_PMIO ; Low=>Enable ,High=>Disable endif;Control_Onchip_By_GPO_Low GE 24 endif;Control_Onchip_By_GPO_Low LE 30 ENDIF; Control_Onchip_By_GPO_Low IFDEF Control_Onchip_By_GPO_High mov si, offset ONBD_Chip_Item call F000_Getitem_Value mov bh,al if Control_Onchip_By_GPO_High LE 7 shl bh,(Control_Onchip_By_GPO_High) mov bl,0FEh rol bl,(Control_Onchip_By_GPO_High) mov cl, 4ch ; Set Onboard Chip En/Disable ; (Special Control by GPIO) call E000_Get_Set_PMIO ; High=>Enable ,Low=>Disable endif;Control_Onchip_By_GPO_High LE 7 if Control_Onchip_By_GPO_High LE 15 if Control_Onchip_By_GPO_High LE 8 shl bh,(Control_Onchip_By_GPO_High - 8) mov bl,0FEh rol bl,(Control_Onchip_By_GPO_High - 8) mov cl, 4dh ; Set Onboard Chip En/Disable ; (Special Control by GPIO) call E000_Get_Set_PMIO ; High=>Enable ,Low=>Disable endif;Control_Onchip_By_GPO_High GE 8 endif;Control_Onchip_By_GPO_High LE 15 if Control_Onchip_By_GPO_High LE 23 if Control_Onchip_By_GPO_High LE 16 shl bh,(Control_Onchip_By_GPO_High - 16) mov bl,0FEh rol bl,(Control_Onchip_By_GPO_High - 16) mov cl, 4eh ; Set Onboard Chip En/Disable ; (Special Control by GPIO) call E000_Get_Set_PMIO ; High=>Enable ,Low=>Disable endif;Control_Onchip_By_GPO_High GE 16 endif;Control_Onchip_By_GPO_High LE 23 if Control_Onchip_By_GPO_High LE 30 if Control_Onchip_By_GPO_High LE 24 shl bh,(Control_Onchip_By_GPO_High - 24) mov bl,0FEh rol bl,(Control_Onchip_By_GPO_High - 24) mov cl, 4fh ; Set Onboard Chip En/Disable ; (Special Control by GPIO) call E000_Get_Set_PMIO ; High=>Enable ,Low=>Disable endif;Control_Onchip_By_GPO_High GE 24 endif;Control_Onchip_By_GPO_High LE 30 ENDIF; Control_Onchip_By_GPO_High endif; VT596 ifdef Check_Fan_USE_GPI IF Check_Fan_USE_GPI LE 7 mov cl, 48h call E000_Get_PMIO test al,(01h shl Check_Fan_USE_GPI) ; 0:normal jnz short Chasis_Fan_Error ; 1:abnormal ENDIF;Check_Fan_USE_GPI LE 7 IF Check_Fan_USE_GPI LE 15 IF Check_Fan_USE_GPI GE 8 mov cl, 49h call E000_Get_PMIO test al,(01h shl (Check_Fan_USE_GPI-8)) ; 0:normal jnz short Chasis_Fan_Error ; 1:abnormal ENDIF;Check_Fan_USE_GPI GE 8 ENDIF;Check_Fan_USE_GPI LE 15 IF Check_Fan_USE_GPI LE 21 IF Check_Fan_USE_GPI GE 16 mov cl, 4Ah call E000_Get_PMIO test al,(01h shl (Check_Fan_USE_GPI-16)) ; 0:normal jnz short Chasis_Fan_Error ; 1:abnormal ENDIF;Check_Fan_USE_GPI GE 16 ENDIF;Check_Fan_USE_GPI LE 21 and byte ptr OEM_Error_CMOS1[bp],NOT OEM_Error_CMOS_Bits1 jmp short @F Chasis_Fan_Error: or byte ptr OEM_Error_CMOS1[bp],OEM_Error_CMOS_Bits1 @@: endif; Check_Fan_USE_GPI ;---------------------------------------; ; Init Registers by Follow Table ; ;---------------------------------------; mov si,offset EGROUP:Ct_Early_Shadow_Tbl @@: mov cx,word ptr cs:[si] mov bx,word ptr cs:[si+2] call _Get_Set_Ct add si,4 cmp si,offset EGROUP:Ct_Early_Shadow_Tbl_End jne short @B ifdef Jumpless_Support JUMPLESS_FOR_CHIPPOST_ASM EQU 1 ;-------- Set CPU Voltage call Change_Jumpless_V endif; Jumpless_Support ;R27 - start ;R37ifdef SndChip_Cntl_USE_ClkGen ;R37 ;R37 extrn SndChip_Item:near ;R37 extrn PCI_Clk_Val:near ;R37 mov si,offset DGROUP:SndChip_Item ;R37 call F000_GetItem_Value ;R37 or al,al ;R37 jz short @F ;R37;R27A Xcall E000_64K_shadow_RW ;R37 F000_call E000_64K_shadow_RW ;R27A ;R37 mov si,offset PCI_Clk_Val ;R37 and byte ptr cs:[si], not SndChip_Cntl_USE_ClkGen ;R37;R27A Xcall E000_64K_shadow_R ;R37 F000_call E000_64K_shadow_R ;R27A ;R37 ;R37 @@: ;R37endif; SndChip_Cntl_USE_ClkGen ;R27 - end ret E000_Ct_Early_Shadow endp ifdef VIA686AIO ;R43 - starts SB_IRQ_Item_TBL: dw (01 SHL 5) dw (01 SHL 7) dw (01 SHL 9) dw (01 SHL 10) endif; VIA686AIO ;R43 - ends Ct_Early_Shadow_Tbl: ;-----------------------; ; index AND, OR ; ;-----------------------; dw VT692+50h ; [5]: Dis/*En I/O Write Deferable db 0FFh,02Ch ; [3]: Dis/*En CPU Read PCI Retry ; [2]: Dis/*En CPU Read PCI Deferred dw VT692+51h ; [7,6]: Dis/*En CPU Read DRAM 0ws for db 0FFh,0C0h ; Back-to-Back Read Transactions dw VT586 + 71h ; Set Subsystem Vendor ID to db 011h,011h ; 1106h(R71/70 map to R2D/2C) dw VT586 + 70h ; db 006h,006h ; ifdef VT686 ;R39 dw VT686 + 077h ;R39 Protect RTC 0Dh write db 0FFH,002h ;R39 endif; VT686 ;R39 dw VT586_IDE + 3Ch ;R03 Reg 3Ch set 0FFh db 0FFh,0FFh ;R03 dw VT586_IDE + 45h ;R03 lock register 3CH db 0FFh,010h ;R03 ;R20 - start ifdef VIA686HM_SUPPORT dw VT586_ACPI + 70h db 0FFh,(VIA686HM_Port AND 0FFh) dw VT586_ACPI + 71h db 0FFh,(VIA686HM_Port shr 8) dw VT586_ACPI + 74h db 0FFh,001h endif; VIA686HM_SUPPORT ;R20 - end ifdef VT686 ;R41 Enable AC-Link Variable-Sample-Rate dw VT686_AC97 + 41h ;R41 On-Demand Mode. db 0FFh,008h ;R41 endif; VT686 ;R41 Ct_Early_Shadow_Tbl_End: ;[]==============================================================[] ; ; E000_Ct_Early_Shadow_1: (POST 0Bh) ; ; Shadowing system and video BIOS to speedup booting. ; ;Saves: ; ; All except ax,dx,es,ds,flag ;Input : None ;Output: None ; ;[Notes] ; ; 1. This routine will shadow system BIOS in early stage ; of POST. ; 2. Stack available ;[]==============================================================[] E000_Ct_Early_Shadow_1 proc far ifdef PCI_BUS ifdef VT586_USB mov cx, VT586_USB + 3ch ;set onchip USB IRQ = 0 call _Set_Ct_Clear endif ;VT586_USB mov cx,VT586 + 47h ; Enable 4D0/4D1 mov bl, 020h ; call _Get_Set_Ct_OR ; ifdef ACPI_Support IFDEF No_ACPI_IRQ_Auto_Assign ;R10 mov si, offset ACPI_option_Item call F000_GetItem_Value or al,al ; ZE : ACPI ; NZ : Not ACPI jnz short No_Assign_ACPI_IRQ ;R10 ifndef No_ACPI_IRQ_Selectable ifdef ACPI_IRQ_Selectable ;R10 mov si, offset Assign_ACPI_IRQ_Item call F000_GetItem_Value or al,al ; ACPI IRQ Set NA ? jz short No_Assign_ACPI_IRQ ; Yes, jmp ! ; AL=0 : NA ; AL=1 : IRQ9 ; AL=2 : IRQ10 ; AL=3 : IRQ11 push ax add al, 8h mov cx, VT586_ACPI + 42h ; Set SCI IRQ according to call _Set_Ct ; Setup setting. pop cx mov bl,01h ; Pre-set IRQ8 shl bl,cl ; IRQ bit map ; CL=1 : 02h (IRQ9) ; CL=2 : 04h (IRQ10) ; CL=3 : 08h (IRQ11) mov dx, 4d1h ;Set ACPI IRQ to level trigger in al, dx or al, bl out dx, al ;R10 else; No_ACPI_IRQ_Selectable else; ACPI_IRQ_Selectable ;R10 mov cx, VT586_ACPI + 42h ;Set SCI IRQ to 9 (fixed temporary) mov al, 09h call _Set_Ct mov dx, 4d1h ;Set IRQ 9 to level trigger in al, dx or al, 02h out dx, al ;R10 endif; No_ACPI_IRQ_Selectable endif; ACPI_IRQ_Selectable ;R10 No_Assign_ACPI_IRQ: ENDIF;No_ACPI_IRQ_Auto_Assign ;R10 endif; ACPI_Support endif; PCI_BUS F000_call F000_Shadow_W push es assume es:DGROUP mov ax, 0f000h mov es, ax Xcall X_check_sdram jz short @f or word ptr es:[SDRAM_CL_Item].ITEMSTAT,ITEMDISABLE ifdef Have_BankInterleave_Item or word ptr es:[SDRAM_BK_Item].ITEMSTAT,ITEMDISABLE endif; Have_BankInterleave_Item @@: ifndef No_Auto_Hidden_Resume_Item ifndef Always_ATX_Power ifndef NO_ATX_Judgement ;R45 mov dx,ACPI_Port + 44h ;R45 in al, dx ;R45 ifdef Control_Cmos_Protect_By_GPIO1 ;R45 test al, 02h ; If AT power ? ;R45 else; Control_Cmos_Protect_By_GPIO1 ;R45 test al, 08h ; If AT power ? ;R45 endif; Control_Cmos_Protect_By_GPIO1 ;R45 jnz short @F ; No,jmp! ;R45 ifdef Have_Keyboard_PowerOn_Item ;R45 or word ptr es:[KB_Item].ITEMSTAT,ITEMDISABLE ;R45 endif; Have_Keyboard_PowerOn_Item ;R45 IFNDEF VT596 ;R45 ifdef Wake_On_EXTSMI0_Support ;R45 or word ptr es:[WO_Item].ITEMSTAT,ITEMDISABLE ;R45 endif; Wake_On_EXTSMI0_Support ;R45 ENDIF; VT596 ;R45 or word ptr es:[Ring_Item].ITEMSTAT,ITEMDISABLE ;R45 or word ptr es:[Alarm_Item].ITEMSTAT,ITEMDISABLE ;R45 or word ptr es:[Alarm_Timer_Date_Item].ITEMSTAT,ITEMDISABLE ;R45 or word ptr es:[Alarm_Timer_Hour_Item].ITEMSTAT,ITEMDISABLE ;R45 or word ptr es:[Alarm_Timer_Min_Item].ITEMSTAT,ITEMDISABLE ;R45 or word ptr es:[Alarm_Timer_Sec_Item].ITEMSTAT,ITEMDISABLE ;R45 @@: ;R45 - starts IFDEF ATX_High_AT_Low_In_GPI if Power_Type_Judge_In_GPI_7_0 NE 00h mov dx, ACPI_Port + 48h in al, dx test al, Power_Type_Judge_In_GPI_7_0 endif;Power_Type_Judge_In_GPI_7_0 NE 00h if Power_Type_Judge_In_GPI_15_8 NE 00h mov dx, ACPI_Port + 49h in al, dx test al, Power_Type_Judge_In_GPI_15_8 endif;Power_Type_Judge_In_GPI_15_8 NE 00h if Power_Type_Judge_In_GPI_21_16 NE 00h mov dx, ACPI_Port + 4Ah in al, dx test al, Power_Type_Judge_In_GPI_21_16 endif;Power_Type_Judge_In_GPI_21_16 NE 00h jnz short Is_ATX_Power ; Yes,jmp! ifdef Have_Keyboard_PowerOn_Item or word ptr es:[KB_Item].ITEMSTAT,ITEMDISABLE endif; Have_Keyboard_PowerOn_Item IFNDEF VT596 ifdef Wake_On_EXTSMI0_Support or word ptr es:[WO_Item].ITEMSTAT,ITEMDISABLE endif; Wake_On_EXTSMI0_Support ENDIF; VT596 or word ptr es:[Ring_Item].ITEMSTAT,ITEMDISABLE or word ptr es:[Alarm_Item].ITEMSTAT,ITEMDISABLE or word ptr es:[Alarm_Timer_Date_Item].ITEMSTAT,ITEMDISABLE or word ptr es:[Alarm_Timer_Hour_Item].ITEMSTAT,ITEMDISABLE or word ptr es:[Alarm_Timer_Min_Item].ITEMSTAT,ITEMDISABLE or word ptr es:[Alarm_Timer_Sec_Item].ITEMSTAT,ITEMDISABLE Is_ATX_Power: ENDIF; ATX_High_AT_Low_In_GPI IFDEF ATX_Low_AT_High_In_GPI ; If ATX power ? if Power_Type_Judge_In_GPI_7_0 NE 00h mov dx, ACPI_Port + 48h in al, dx test al, Power_Type_Judge_In_GPI_7_0 endif;Power_Type_Judge_In_GPI_7_0 NE 00h if Power_Type_Judge_In_GPI_15_8 NE 00h mov dx, ACPI_Port + 49h in al, dx test al, Power_Type_Judge_In_GPI_15_8 endif;Power_Type_Judge_In_GPI_15_8 NE 00h if Power_Type_Judge_In_GPI_21_16 NE 00h mov dx, ACPI_Port + 4Ah in al, dx test al, Power_Type_Judge_In_GPI_21_16 endif;Power_Type_Judge_In_GPI_21_16 NE 00h jz short Is_ATX_Power ; Yes,jmp! ifdef Have_Keyboard_PowerOn_Item or word ptr es:[KB_Item].ITEMSTAT,ITEMDISABLE endif; Have_Keyboard_PowerOn_Item IFNDEF VT596 ifdef Wake_On_EXTSMI0_Support or word ptr es:[WO_Item].ITEMSTAT,ITEMDISABLE endif; Wake_On_EXTSMI0_Support ENDIF; VT596 or word ptr es:[Ring_Item].ITEMSTAT,ITEMDISABLE or word ptr es:[Alarm_Item].ITEMSTAT,ITEMDISABLE or word ptr es:[Alarm_Timer_Date_Item].ITEMSTAT,ITEMDISABLE or word ptr es:[Alarm_Timer_Hour_Item].ITEMSTAT,ITEMDISABLE or word ptr es:[Alarm_Timer_Min_Item].ITEMSTAT,ITEMDISABLE or word ptr es:[Alarm_Timer_Sec_Item].ITEMSTAT,ITEMDISABLE Is_ATX_Power: ENDIF; ATX_Low_AT_High_In_GPI ;R45 - ends endif; NO_ATX_Judgement endif; Always_ATX_Power endif; No_Auto_Hidden_Resume_Item ifdef Have_BankInterleave_Item ifdef Have_Page_Mode_Item ifdef Disable_Page_Mode_Item_When_Over_100MHz XCall X_If_100MHz_DRAM_Clock ; if 100MHz ? jnc short @f ; No, jmp ! or word ptr es:[DRAM_Page_Mode_Item].ITEMSTAT,ITEMDISABLE @@: endif; Disable_Page_Mode_Item_When_Over_100MHz endif; Have_Page_Mode_Item endif; Have_BankInterleave_Item mov di,offset Bank01_Dram_Timing_Val mov si,offset Bank01_Dram_Timing_Val_ mov bl,02h call Change_DRAM_Timing_Item_String mov di,offset Bank23_Dram_Timing_Val mov si,offset Bank23_Dram_Timing_Val_ mov bl,08h call Change_DRAM_Timing_Item_String mov di,offset Bank45_Dram_Timing_Val mov si,offset Bank45_Dram_Timing_Val_ mov bl,20h call Change_DRAM_Timing_Item_String mov di,offset Bank67_Dram_Timing_Val mov si,offset Bank67_Dram_Timing_Val_ mov bl,80h call Change_DRAM_Timing_Item_String ;R44 - starts ifndef No_Have_DRAM_Async_Item ;R44A mov cx,VT692 + 08h call _Get_Ct cmp al, 40h jb short Not_133Mhz_Support push es push ds mov ax,0F000h mov es,ax mov ax,0E000h mov ds,ax mov si,offset HostCLK_Sub_33 mov di,offset DRAM_Async_Val_ mov cx,8 rep movsb pop ds pop es Not_133Mhz_Support: endif ;No_Have_DRAM_Async_Item ;R44A ;R44 - ends F000_call F000_Shadow_R pop es ;R01 - starts ifdef OEM1_GPO_CNTL ;R19 extrn E000_GPO_Pin_High:near extrn OEM1_GPO_CNTL_Item:near mov si,offset DGROUP:OEM1_GPO_CNTL_Item call F000_GetItem_Value or al,al jz short @F mov bl,OEM1_GPO_CNTL call E000_GPO_Pin_High @@: endif; OEM1_GPO_CNTL ifdef OEM2_GPO_CNTL ;R19 extrn E000_GPO_Pin_High:near extrn OEM2_GPO_CNTL_Item:near mov si,offset DGROUP:OEM2_GPO_CNTL_Item call F000_GetItem_Value or al,al jnz short @F mov bl,OEM2_GPO_CNTL call E000_GPO_Pin_High @@: endif; OEM2_GPO_CNTL ifdef OEM3_GPO_CNTL ;R19 extrn E000_GPO_Pin_High:near extrn OEM3_GPO_CNTL_Item:near mov si,offset DGROUP:OEM3_GPO_CNTL_Item call F000_GetItem_Value or al,al jz short @F mov bl,OEM3_GPO_CNTL call E000_GPO_Pin_High @@: endif; OEM3_GPO_CNTL ;R01 - ends ret E000_Ct_Early_Shadow_1 endp HostCLK_Sub_33 db 'HCLK-33M' ;R44 ;[]==============================================================[] ; Change_DRAM_Timing_Item_String: ;Saves: ; All except ax,dx,es,ds,flag ;Input : BL : 02h => Bank0,1 ; 08h => Bank2,3 ; 20h => Bank4,5 ; DI : ;Output: None ; ;[Notes] ; ; 1. This routine will shadow system BIOS in early stage ; of POST. ; 2. Stack available ;[]==============================================================[] Change_DRAM_Timing_Item_String Proc Near mov bh,bl ;R08 shr bl,1 ;R08 or bh,bl ;R08 mov cx, VT692 + 60h call _Get_Ct ;R08 test al,bl and al,bh ;R08 cmp al,bl ;R08 ;R08 jz short Bank01_Not_SDRAM jnz short Bank_Not_EDO ;R08 push ds assume ds:DGROUP mov ax, 0f000h mov ds, ax mov ax,si sub ax,di mov bl,6 div bl xor ah,ah dec al mov cx,ax rep movsb inc di inc si mov cx,ax rep movsb pop ds ;R08 Bank01_Not_SDRAM: Bank_Not_EDO: ;R08 ret Change_DRAM_Timing_Item_String Endp ifdef ACPI_Support IFDEF ACPI_IRQ_Selectable ;R10 ;[]==============================================================[] ;Ct_Update_PNP_IRQ_Map: ; ; Update PNP IRQ Map by chipset request. (Ex : the IRQ of ACPI SCI) ; ;Save : all register ; ;Input : AX : available PNP IRQ bit map ;Output: AX : available PNP IRQ bit map ; ;Note : 1. You must save all register. ; ;[]==============================================================[] Public Ct_Update_PNP_IRQ_Map Ct_Update_PNP_IRQ_Map Proc Near pushad mov cx, VT586_ACPI + 42h ; Get SCI IRQ call _Get_Ct and al,0Fh ;R18A mov cl,al mov bx,0FFFEh ; Set can't be used in PNP ISA rol bx,cl mov gs,bx popad push bx mov bx,gs and ah,bh pop bx ret Ct_Update_PNP_IRQ_Map Endp ENDIF;ACPI_IRQ_Selectable ;R10 ifdef Special_ACPI_Table_Update ;[]========================================================================[] ; Ct_ACPI_Update: Routing IRQ11 or 10 or 9 to SCI and update relative register ; ; Exit: None ; ; Destroy : None ; ;[]========================================================================[] Public Ct_ACPI_Table_Update Ct_ACPI_Table_Update Proc Near pushad mov cx, VT586_ACPI + 42h ; Get SCI IRQ call _Get_Ct and al,0Fh ;R18 xor ah,ah mov esi, ACPISeg add esi, offset FACP_Pointer ;FACP mov edi, dword ptr ds:[esi] mov word ptr es:[edi]+46, ax ; Set SCI IRQ to FACP ;R10 mov ax,word ptr es:[edi]+46 ; popad ret Ct_ACPI_Table_Update Endp endif; Special_ACPI_Table_Update endif; ACPI_Support ifdef CLEAR_PASSWORD_SUPPORT ;[]==============================================================[] ;E000_Ck_Password_Switch: (POST 0Eh) ; Some board maker design a password switch to clear password ; setting. You can check the switch here, and disable password ; checking and display any messages if switch on. ;Save : all but flag ;Input : none ;Output: none ;Note : 1. This routine is customerization issue. ;[]==============================================================[] E000_Ck_Password_Switch proc Far ;---------------------------------------; ; Check If Jumper set Clear Password ; ;---------------------------------------; IFDEF VT596 ifdef Clear_Password_By_GPI_Low IF Clear_Password_By_GPI_Low LE 7 mov cl, 48h call E000_Get_PMIO test al,(01h shl Clear_Password_By_GPI_Low) jnz short Pwd_Enable ENDIF; Clear_Password_By_GPI_Low LE 7 IF Clear_Password_By_GPI_Low LE 15 if Clear_Password_By_GPI_Low GE 8 mov cl, 49h call E000_Get_PMIO test al,(01h shl (Clear_Password_By_GPI_Low-8)) jnz short Pwd_Enable endif; Clear_Password_By_GPI_Low GE 8 ENDIF; Clear_Password_By_GPI_Low LE 15 IF Clear_Password_By_GPI_Low LE 21 if Clear_Password_By_GPI_Low GE 16 mov cl, 4Ah call E000_Get_PMIO test al,(01h shl (Clear_Password_By_GPI_Low-16)) jnz short Pwd_Enable endif; Clear_Password_By_GPI_Low GE 16 ENDIF; Clear_Password_By_GPI_Low LE 21 endif; Clear_Password_By_GPI_Low ifdef Clear_Password_By_GPI_High IF Clear_Password_By_GPI_High LE 7 mov cl, 48h call E000_Get_PMIO test al,(01h shl Clear_Password_By_GPI_High) jz short Pwd_Enable ENDIF; Clear_Password_By_GPI_High LE 7 IF Clear_Password_By_GPI_High LE 15 if Clear_Password_By_GPI_High GE 8 mov cl, 49h call E000_Get_PMIO test al,(01h shl (Clear_Password_By_GPI_High-8)) jz short Pwd_Enable endif; Clear_Password_By_GPI_High GE 8 ENDIF; Clear_Password_By_GPI_High LE 15 IF Clear_Password_By_GPI_High LE 21 if Clear_Password_By_GPI_High GE 16 mov cl, 4Ah call E000_Get_PMIO test al,(01h shl (Clear_Password_By_GPI_High-16)) jz short Pwd_Enable endif; Clear_Password_By_GPI_High GE 16 ENDIF; Clear_Password_By_GPI_High LE 21 endif; Clear_Password_By_GPI_High ENDIF;VT596 IFDEF Clear_Password_By_KB_GPI extrn Read_Input_Port:near call Read_Input_Port ;AH - port value jc short Pwd_Enable test ah,00100000b ;low to clear password jnz short Pwd_Enable ENDIF;Clear_Password_By_KB_GPI ;-----------------------; ; Clear Password ; ;-----------------------; xor ax,ax and byte ptr CMOS11[bp],NOT 02H ; Clear user password IFDEF Double_Password call far ptr E000_Ct_User_Password_Location ; Read CMOS location mov byte ptr [bp+si],al ; Clear supervisor pwd ENDIF;Double_Password push cs ; DS = CS pop ds mov si,offset Pwd_String ; Show Message call F000_Display_String ; ;-----------------------; ; Don't Clear Password ; ;-----------------------; Pwd_Enable: ret E000_Ck_Password_Switch endp Pwd_String db 'Password Cleared By Jumper !',NEWLINE,0 endif; CLEAR_PASSWORD_SUPPORT ifdef Double_Password ;[]========================================================================[] ;Procedure: E000_Ct_User_Password_Location ; ;Function : Claim the CMOS locations for two-layer password operation ; ;Input : None ; ;Output : DI - First CMOS location to store hashed password, this need ; 2 bytes of CMOS ; SI - CMOS location to save password setting flag ; DL - Mask byte for checking password settging ; ; ;Registers: all except DI,SI and DL ; ;Note : 1. stack available ; 2. The programmer should implement this routine to support ; two-layer password. ; 3. The routine must offer 3 bytes of CMOS to caller. ;[]========================================================================[] E000_Ct_User_Password_Location Proc Far mov di,63h ;CMOS 64h, 65h for hashed user password mov si,62h ;CMOS 66h bit 0 = 0 user password not set mov dl,01h ; 1 user password set ret E000_Ct_User_Password_Location Endp endif; Double_Password ifdef JUMPER_CMOS_CLEAR_SUPPORT ;[]==============================================================[] ; ;Ct_Cmos_Jumper_Chk: (POST 0Bh) ; ; Clear CMOS ; ;Saves: ; ; All except ax,dx,es,ds,flag ;Input : None ;Output: Flag: carry=0: clear cmos ; carry=1:no clear cmos ;[Notes] ; 1. Stack available ;[]==============================================================[] align 4 public Ct_Cmos_Jumper_Chk Ct_Cmos_Jumper_Chk proc near IFDEF VT596 ifdef CMOS_Clear_Support_Use_GPI_Low IF CMOS_Clear_Support_Use_GPI_Low LE 7 mov cl, 48h call E000_Get_PMIO test al,(01h shl CMOS_Clear_Support_Use_GPI_Low) jnz short no_clear_cmos ENDIF; CMOS_Clear_Support_Use_GPI_Low LE 7 IF CMOS_Clear_Support_Use_GPI_Low LE 15 if CMOS_Clear_Support_Use_GPI_Low GE 8 mov cl, 49h call E000_Get_PMIO test al,(01h shl (CMOS_Clear_Support_Use_GPI_Low-8)) jnz short no_clear_cmos endif; CMOS_Clear_Support_Use_GPI_Low GE 8 ENDIF; CMOS_Clear_Support_Use_GPI_Low LE 15 IF CMOS_Clear_Support_Use_GPI_Low LE 21 if CMOS_Clear_Support_Use_GPI_Low GE 16 mov cl, 4Ah call E000_Get_PMIO test al,(01h shl (CMOS_Clear_Support_Use_GPI_Low-16)) jnz short no_clear_cmos endif; CMOS_Clear_Support_Use_GPI_Low GE 16 ENDIF; CMOS_Clear_Support_Use_GPI_Low LE 21 endif; CMOS_Clear_Support_Use_GPI_Low ifdef CMOS_Clear_Support_Use_GPI_High IF CMOS_Clear_Support_Use_GPI_High LE 7 mov cl, 48h call E000_Get_PMIO test al,(01h shl CMOS_Clear_Support_Use_GPI_High) jz short no_clear_cmos ENDIF; CMOS_Clear_Support_Use_GPI_High LE 7 IF CMOS_Clear_Support_Use_GPI_High LE 15 if CMOS_Clear_Support_Use_GPI_High GE 8 mov cl, 49h call E000_Get_PMIO test al,(01h shl (CMOS_Clear_Support_Use_GPI_High-8)) jz short no_clear_cmos endif; CMOS_Clear_Support_Use_GPI_High GE 8 ENDIF; CMOS_Clear_Support_Use_GPI_High LE 15 IF CMOS_Clear_Support_Use_GPI_High LE 21 if CMOS_Clear_Support_Use_GPI_High GE 16 mov cl, 4Ah call E000_Get_PMIO test al,(01h shl (CMOS_Clear_Support_Use_GPI_High-16)) jz short no_clear_cmos endif; CMOS_Clear_Support_Use_GPI_High GE 16 ENDIF; CMOS_Clear_Support_Use_GPI_High LE 21 endif; CMOS_Clear_Support_Use_GPI_High ENDIF;VT596 stc ret no_clear_cmos: clc ret Ct_Cmos_Jumper_Chk endp endif; JUMPER_CMOS_CLEAR_SUPPORT ifdef Jumpless_Support include JUMPLESS.INC endif; Jumpless_Support ifdef Check_FAN_Use_GPI public OEM_Error_Special_String1 OEM_Error_Special_String1 db 'Ventilator fan failure : PC may overheat.' db NEWLINE db 'Switch off PC and verify for connector.',0 endif; Check_FAN_Use_GPI ;R07 - starts ;R07A ifdef CAS_Latency_Error_String ;R07A public OEM_Error_Special_String2 ;R07A OEM_Error_Special_String2 db 'WARRING :Your SDRAM dont have SPD or can not support 2T.' ;R07A db NEWLINE ;R07A db 'Suggest :Please set your CAS Latency=3T.',0 ;R07A endif; CAS_Latency_Error_String ;R07A ifdef CAS_Latency_Error_String ifndef No_Suggested_SDRAM_CL ;R07A - starts E000_Show_CAS_Latency_Error_String Proc Far lea si,Suggested_CL_3T_Str cmp di,1 jz short @F lea si,Suggested_CL_2T_Str @@: push si lea si,Suggested_CL_Str extrn F000_Vcrlf:near extrn Disp_Str_In_post:near call F000_Vcrlf call Disp_Str_In_post pop si call Disp_Str_In_post ret E000_Show_CAS_Latency_Error_String Endp Suggested_CL_Str db V_NORMAL,' Suggested SDRAM CAS Latency Time is ',V_HILITE,'" ',0 Suggested_CL_2T_Str db '2 "',V_NORMAL,0 Suggested_CL_3T_Str db '3 "',V_NORMAL,0 endif; No_Suggested_SDRAM_CL ;R07A - ends ;R07 - ends ifndef No_Suggested_DRAM_Clock ;R46 - starts E000_Show_DRAM_Clock_Error_String Proc Far extrn F000_Vcrlf:near call F000_Vcrlf lea si,Suggested_DCL_Str extrn Disp_Str_In_post:near call Disp_Str_In_post lea si,Suggested_DCL_133_Str cmp bl,4 jz short @F lea si,Suggested_DCL_100_Str cmp bl,2 jz short @F lea si,Suggested_DCL_66_Str @@: call Disp_Str_In_post ret E000_Show_DRAM_Clock_Error_String Endp Suggested_DCL_Str db V_NORMAL,' Suggested DRAM Clock is ',V_HILITE,'" ',0 Suggested_DCL_66_Str db '66 "',V_NORMAL,0 Suggested_DCL_100_Str db '100 "',V_NORMAL,0 Suggested_DCL_133_Str db '133 "',V_NORMAL,0 endif; No_Suggested_SDRAM_CL ;R46 - ends ifdef Password_ON_NOW_SUPPORT ifndef RTC_BANK2_CAN_NOT_USE ifndef KB_PassWord_Start_Loc KB_PassWord_Start_Loc equ 70h endif; KB_PassWord_Start_Loc Public Ct_KB_Password_Location Ct_KB_Password_Location Proc Near pushad ifdef NS351 mov cx, 8 ; set length counter else; NS351 mov cx, 5 ; set length counter endif; NS351 xor bl, bl xor si, si ;index to point to KEYIN_BUF[bp] ;Use second blank cmos store KB PowerOn ;PassWord %default begin 70h - 75h mov al, byte ptr KB_PassWord_Start_Loc Save_Next_Pass_Byte: mov ah, KEYIN_BUF[bp+si] add bl, ah push ax call F000_Set_Cmos2 pop ax inc al inc si loop short Save_Next_Pass_Byte mov ah, bl call F000_Set_Cmos2 popad ret Ct_KB_Password_Location Endp Public Ct_KB_Password_Fail Ct_KB_Password_Fail Proc Near pushad ifdef NS351 mov cx, 9 ; set length counter else; NS351 mov cx, 6 ; set length counter endif; NS351 xor si, si ;index to point to KEYIN_BUF[bp] ;Use second blank cmos store KB PowerOn ;PassWord %default begin 70h - 75h mov al, byte ptr KB_PassWord_Start_Loc Save_Next_Pass_Byte1: mov ah, 0aah push ax call F000_Set_Cmos2 pop ax inc al inc si loop short Save_Next_Pass_Byte1 popad ret Ct_KB_Password_Fail Endp Public Get_Password_Value Get_Password_Value Proc Near mov al, byte ptr KB_PassWord_Start_Loc add al, dl call F000_Get_Cmos2 mov dh, al ret Get_Password_Value Endp Public Get_Password_Value_OK Get_Password_Value_OK Proc Near pushad ifdef NS351 mov cx, 8 ; set length counter else; NS351 mov cx, 5 ; set length counter endif; NS351 xor bx, bx mov al, byte ptr KB_PassWord_Start_Loc Save_Next_Pass_Byte2: push ax call F000_Get_Cmos2 xor ah, ah add bx, ax pop ax inc al loop short Save_Next_Pass_Byte2 call F000_Get_Cmos2 or al, al jnz short @f or bh, bh jz short Fail_exit @@: cmp al, bl jne short Fail_exit clc popad ret Fail_exit: stc popad ret Get_Password_Value_OK Endp endif; RTC_BANK2_CAN_NOT_USE endif; Password_ON_NOW_SUPPORT ifdef NEW_IDE_MODE_3 ;[]==============================================================[] ; ; E000_Ct_Set_IDE_Timing: ; ; Programing I/O chip registre for IDE PIO mode 3 support ; ; SAVES : all ; ; ENTRY : IDE_PARM_Flag[bp] : ; Bit 0 - 3 = drive 0-3 support PIO mode 3 if bit set to 1 ; ; EXIT : None ; ; NOTE : 1. Stack available ; ;[]==============================================================[] IdeMode_Item: dw offset IdeA_Mode_Item dw offset IdeB_Mode_Item ifndef ONCHIP_2ND_ALWAYS_DISABLE ifdef Support_4_IDE ;R11 dw offset IdeC_Mode_Item dw offset IdeD_Mode_Item endif; Support_4_IDE ;R11 endif; ONCHIP_2ND_ALWAYS_DISABLE public E000_Ct_Set_IDE_Timing E000_Ct_Set_IDE_Timing proc far push ds push es mov ax,G_RAM mov ds,ax assume ds:G_RAM ;Read setup value for IDE mode, this value will override the value by auto- ;detection of HDD mov di,offset IdeMode_Item xor bx,bx ifndef ONCHIP_2ND_ALWAYS_DISABLE mov cx,4 ;total 4 drives else; ONCHIP_2ND_ALWAYS_DISABLE mov cx,2 ;total 2 drives endif; ONCHIP_2ND_ALWAYS_DISABLE Next_IdeMode: mov si,cs:[di] call F000_GetItem_Value or al,al ;auto ? jz short @F dec al mov si,bx mov byte ptr HDD_0_MODE[bp+si],al ;restore mode @@: add di,2 inc bx loop short Next_IdeMode mov bx,offset PCI_Frequency_100MHz XCall X_If_100MHz_DRAM_Clock ; if 100MHz ? jc short @F mov bx,offset PCI_Frequency_33MHz @@: ;Program IDE timing according to PCI clock and IDE transfer mode ;register 4bh - for drive 0 ; 4ah - for drive 1 ; 49h - for drive 2 ; 48h - for drive 3 mov si,HDD_0_MODE ;start from drive 0 mov cx,VT586_IDE+4bh Prg_Next_Drive: push bx mov ah,0A8H mov al,[bp+si] or al,al ;mode 0 ? jz short Mode0 ;don't program for mode 0 xor ah,ah test cl,01h ; If Slave jnz short @f ; => set lower mode. dec al @@: add bx,ax mov ah,cs:[bx] ;get timing Mode0: mov al,ah push cx call _Set_Ct pop cx pop bx dec cl ;next register inc si ;next drive type cmp cl,48h jae short Prg_Next_Drive ifdef Ultra_DMA33_support mov bx,offset UltraDMA_Mode_100MHz XCall X_If_100MHz_DRAM_Clock ; if 100MHz ? ifdef Disable_Ultra_DMA_When_100MHz jc short Ultra_DMA33_support_Exit else; Disable_Ultra_DMA_When_100MHz jc short @F endif; Disable_Ultra_DMA_When_100MHz mov bx,offset UltraDMA_Mode @@: mov si,HDD_0_UltraDMA ;start from drive 0 mov cx,VT586_IDE+53h Prg_Next_DMA: push bx mov ah, 03h mov al,[bp+si] cmp al, 0ffh ;doesn't support sync DMA? jz short UltraMode0 ;don't program for mode 0 ;R17 pushad ;R17 mov cx,VT586_IDE+43h ; Disable => R43[7](0:Disable) ;R17 mov bl, 80h ; "Clear DMA Write Flag by ;R17 call _Get_Set_Ct_OR ; IO Write to Port 1F7/177" ;R17 popad ;R30 - starts ifdef UltraDMA_MaxMode IF UltraDMA_MaxMode GT 2 ifdef UltraDMA66_Not_See_Cable ;-----------------------------------------------; ; See Another HDD of the same CH is UDMA66 ? ; ;-----------------------------------------------; ; CL = 53 : CH0 Master ; CL = 52 : CH0 Slave ; CL = 51 : CH1 Master ; CL = 50 : CH1 Slave test cl,01h ; If Slave HDD ? jz short Slave_HDD_ ;=== Master ===; cmp byte ptr [bp+si+1],0FFh jz short Test_This_HDD_ cmp byte ptr [bp+si+1],04h jae short Set_UDMA66_Timing Slave_HDD_: ;=== Slave ===; cmp byte ptr [bp+si-1],0FFh jz short Test_This_HDD_ cmp byte ptr [bp+si-1],04h jae short Set_UDMA66_Timing ;-----------------------------------------------; ; See This HDD is UDMA66 ? ; ;-----------------------------------------------; Test_This_HDD_: cmp al,4 ; If UDMA Mode 4 HDD ? jae short Set_UDMA66_Timing ; Yes, Jmp ! else; UltraDMA66_Not_See_Cable ;-----------------------------------------------; ; If Cable of This Channel is Support UDMA66 ? ; ;-----------------------------------------------; ; CL = 53 : CH0 Master ; CL = 52 : CH0 Slave ; CL = 51 : CH1 Master ; CL = 50 : CH1 Slave mov dl,53h sub dl,cl call Ct_IDE_Interface_Status jc short Not_UDMA66_ endif;UltraDMA66_Not_See_Cable Set_UDMA66_Timing: add bx, UDMA66_Tbl_Offset ; Assign UDMA66 Table pushad and cl,0FEh mov bl,08h call _Get_Set_Ct_OR popad Not_UDMA66_: endif ;UltraDMA_MaxMode endif ;UltraDMA_MaxMode ;R30 - ends xor ah,ah add bx,ax mov ah,cs:[bx] ;get timing ifdef VT596 or ah, 0C0h else; VT596 or ah, 040h endif; VT596 UltraMode0: ;R42 mov al,ah ;R42 push cx ;R42 call _Set_Ct ;R42 pop cx mov bh,ah ;R42 mov bl,08h ;R42 call _Get_Set_Ct ;R42 pop bx dec cl ;next register inc si ;next drive type cmp cl,50h jae short Prg_Next_DMA Ultra_DMA33_support_Exit: endif ;Ultra_DMA33_support ifdef VT596 mov cx,VT586_IDE+44h ; Enable => mov bl,04h ; Add Dummy FIFO Push After call _Get_Set_Ct_OR ; End of Transfer endif; VT596 pop es pop ds ret E000_Ct_Set_IDE_Timing endp ;R30 - starts ifdef UltraDMA_MaxMode if UltraDMA_MaxMode GT 2 ;[]==============================================================[] ; Entry : DL = drive number (0,1,2,3) ; Exit : NC = connect new interface ; : CY = No connect new interface ;[]==============================================================[] public Ct_IDE_Interface_Status Ct_IDE_Interface_Status: pusha test dl,2 ;check secondary channel jnz short Check_Channel2 ;Yes,jump to channel 2 ;-------------------------------; ; Detect Channel 1 UltraDMA66 ; ;-------------------------------; ifdef CH1_UltraDMA66_High_In_GPI mov bl,CH1_UltraDMA66_High_In_GPI call E000_Read_GPI_Pin clc ; Channel 1 support UltraDMA66 ! jnz short CIIS_ret endif; CH1_UltraDMA66_High_In_GPI ifdef CH1_UltraDMA66_Low_In_GPI mov bl,CH1_UltraDMA66_Low_In_GPI call E000_Read_GPI_Pin clc ; Channel 1 support UltraDMA66 ! jz short CIIS_ret endif; CH1_UltraDMA66_Low_In_GPI ifdef CH1_Always_Support_UltraDMA66 clc ; Channel 1 support UltraDMA66 ! jz short CIIS_ret endif; CH1_Always_Support_UltraDMA66 stc ; Channel 1 Not Support UltraDMA66. jmp short CIIS_ret Check_Channel2: ;-------------------------------; ; Detect Channel 2 UltraDMA66 ; ;-------------------------------; ifdef CH2_UltraDMA66_High_In_GPI mov bl,CH2_UltraDMA66_High_In_GPI call E000_Read_GPI_Pin clc ; Channel 2 support UltraDMA66 ! jnz short CIIS_ret endif; CH2_UltraDMA66_High_In_GPI ifdef CH2_UltraDMA66_Low_In_GPI mov bl,CH2_UltraDMA66_Low_In_GPI call E000_Read_GPI_Pin clc ; Channel 2 support UltraDMA66 ! jz short CIIS_ret endif; CH2_UltraDMA66_Low_In_GPI ifdef CH2_Always_Support_UltraDMA66 clc ; Channel 2 support UltraDMA66 ! jz short CIIS_ret endif; CH2_Always_Support_UltraDMA66 stc ; Channel 2 Not Support UltraDMA66. CIIS_ret: popa ret endif ;UltraDMA_MaxMode endif ;UltraDMA_MaxMode ;R30 - ends ifdef E000_IDE_Special_Do ;[]==============================================================[] ; ; E000_Ct_IDE_Special_Do: ; ; IDE Special Do after Detect IDE ; ; SAVES : all ; ; ENTRY : HDD_0_Ultra[bp] / HDD_0_MODE[bp] ; EXIT : None ; ; NOTE : 1. Stack available ;[]==============================================================[] IFDEF WD_IDE_Special_Do HDD_Str : HDD_Str_End db 'WD' HDD_Str_Len EQU $ - HDD_Str_End ENDIF;WD_IDE_Special_Do public E000_Ct_IDE_Special_Do E000_Ct_IDE_Special_Do: push es pusha push cs pop es IFDEF WD_IDE_Special_Do ;-------------------------------; ; Special IDE for WD HDD ; ;-------------------------------; push si lea di,HDD_Str @@: cld mov cx,HDD_Str_Len rep cmpsb je short Disable_IO_Refresh lea bx,HDD_Str_End cmp di,bx jae short No_Disable_IO_Refresh mov cx,HDD_Str_Len-1 add di,cx dec si jmp short @b Disable_IO_Refresh: mov cx, VT586 + 41h ; Disable I/O Refresh mov bl,not 01h ; call _Get_Set_Ct_AND ; No_Disable_IO_Refresh: pop si ENDIF;WD_IDE_Special_Do IFNDEF UltraMode2_No_Set_Mode1 ;---------------------------------------; ; Always UltraMode2 Set Mode1 For 596 ; ;---------------------------------------; assume es:DGROUP mov ax, 0F000h mov es, ax test byte ptr es:[UltraMode2_Set_Mode1_Status+5],01h jz short No_UltraMode2_Set_Mode1 mov cx, VT586_IDE + 08h ;R04A call _Get_Ct ;R04A cmp al,06h ;R04A jae short No_UltraMode2_Set_Mode1 ;R04A ;=======================; ; UltraMode2 set Mode1 ; ;=======================; mov al,dl ;get drive number and al,03H ;valid bits movzx si,al add si,HDD_0_UltraDMA cmp byte ptr [bp+si],2 jnz short No_UltraMode2_Set_Mode1 mov byte ptr [bp+si],1 ;Force set mode 1 No_UltraMode2_Set_Mode1: ENDIF; UltraMode2_No_Set_Mode1 IFNDEF Dont_Disable_IDEPreFetch_When_CDROM ;R16 test byte ptr CDROM_Exist_Flag[bp],PM_CDROM+PS_CDROM+SM_CDROM+SS_CDROM ;R16 jz short No_CDRAM_Used ;R16 mov cx, VT586_IDE+41h ;R16 mov bl, not 0F0h ;R16 call _Get_Set_Ct_AND ;R16 No_CDRAM_Used: ;R16 ENDIF; Dont_Disable_IDEPreFetch_When_CDROM ;R16 popa pop es ret endif; E000_IDE_Special_Do ;---------------------------------------------------------------; ; PIO Mode : ; ; Mode 0 Mode1 Mode 2 Mode 3 Mode 4 ; ;---------------------------------------------------------------; PCI_Frequency_100MHz: ifndef Hsing_Mode3_Mode4_IDE ifndef Gemlight_Special_IDE_Timing ifndef Free_Special_IDE_Timing db 0A8H, 65H, 065H, 031H, 021H ;Standard endif; Free_Special_IDE_Timing endif; Gemlight_Special_IDE_Timing endif; Hsing_Mode3_Mode4_IDE ifdef Free_Special_IDE_Timing db 0A8H, 0A8H, 065H, 065H, 031H ;Free endif; Free_Special_IDE_Timing ifdef Gemlight_Special_IDE_Timing db 0A8H, 0A8H, 065H, 065H, 031H ;Gemlight endif; Gemlight_Special_IDE_Timing ifdef Hsing_Mode3_Mode4_IDE db 0A8H, 0A8H, 065H, 065H, 031H ;Hsing endif; Hsing_Mode3_Mode4_IDE PCI_Frequency_33MHz: PCI_Frequency_25MHz: ifndef Hsing_Mode3_Mode4_IDE ifndef Mycomp_Mode4_IDE ifndef Gemlight_MODE3_IDE ifdef LuckyStar_MODE3_IDE db 0A8H, 65H, 065H, 031H, 031H ;Luckstar else ;LuckyStar_MODE3_IDE db 0A8H, 65H, 065H, 031H, 020H ;Standard endif ;LuckyStar_MODE3_IDE else ;Gemlight_MODE3_IDE db 0A8H, 65H, 065H, 065H, 020H ;Gemlight endif ;Gemlight_MODE3_IDE else; Mycomp_Mode4_IDE db 0A8H, 65H, 065H, 065H, 021H ;Mycomp endif; Mycomp_Mode4_IDE else; Hsing_Mode3_Mode4_IDE db 0A8H, 65H, 065H, 042H, 031H ;Hsing endif; Hsing_Mode3_Mode4_IDE ;R30 ifdef Ultra_DMA33_support ;R30 ;-----------------------------------------------; ;R30 ; UltraDMA Mode : ; ;R30 ; mode mode 0 mode 1 mode2 ; ;R30 ;-----------------------------------------------; ;R30 UltraDMA_Mode: ;R30 db 02H, 01H, 00H ;R30 UltraDMA_Mode_100MHz: ;R30 db 02H, 02H, 01H ; Standard ;R30 endif ;Ultra_DMA33_support ;R30 - starts ifdef Ultra_DMA33_support ;---------------; ; Ultra DMA 33 ; ;---------------; ; mode mode 0 mode 1 mode2 Dummy Dummy ; UltraDMA_Mode: db 02H, 01H, 00H, 0FFh, 0FFh UltraDMA_Mode_100MHz: db 02H, 02H, 01H, 0FFh, 0FFh ; Standard endif ;Ultra_DMA33_support ifdef UltraDMA_MaxMode if UltraDMA_MaxMode GT 2 UDMA66_Tbl_Offset = $ - UltraDMA_Mode ;---------------; ; Ultra DMA 66 ; ;---------------; ; Mode 0 Mode1 Mode 2 Mode 3 Mode 4 UltraDMA66_Mode: db 006H, 004H, 002H, 001H, 000H ; Normal UltraDMA66_Mode_100MHz: db 006H, 006H, 004H, 002H, 001H ; Normal ENDIF;UltraDMA_MaxMode GT 2 endif;UltraDMA_MaxMode ;R30 - ends endif; NEW_IDE_MODE_3 ECODE ENDS END